IP Library Granted Patent US 7,897,459
Granted Patent B2
US 7,897,459 · App. 11/857,286 · Granted Mar 1, 2011

Semiconductor device and manufacturing method thereof

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Quick Facts
Patent No.
US 7,897,459
App. No.
11/857,286
Granted
Mar 1, 2011
Kind
B2
Abstract

A through electrode is formed prior to fabricating a semiconductor device by using a standard manufacturing method. Aside face of the through electrode is insulated from a semiconductor substrate by an insulating film, while the top face thereof is covered with a protective insulating film. These insulating films covering the through electrode protect a conductor of the through electrode and prevent emission of a contaminant from the conductor. Standard manufacturing conditions can be applied without change.

Claims (33)

1. A method of manufacturing a semiconductor device having a through electrode, comprising:

forming a trench for the through electrode in a semiconductor substrate;

forming stacked insulating films on a top face of the semiconductor substrate and a side face of the trench;

filling the trench with a conductor after forming the stacked insulating films;

etching the conductor to form a recess so that a top face of the conductor is at a lower level than a top face of the stacked insulating films;

removing a part of the stacked insulating films on the top face of the semiconductor substrate to expose an isolation region of the semiconductor substrate;

removing a top portion of the conductor and the semiconductor substrate of the isolation region simultaneously; and

forming a protective insulating film on the conductor which is remained in the trench after removing the top portion of the conductor.

2. The method according to claim 1 , wherein forming the stacked insulating films comprises:

forming a first oxide film on the semiconductor substrate;

forming a nitride film on the first oxide film; and,

forming a second oxide film on the nitride film.

3. The method according to claim 2 , further comprising:

removing the second oxide film over the top face of the semiconductor substrate after etching the conductor to form the recess,

wherein the nitride film and the first oxide film are used as a mask to remove the top portion of the conductor and the semiconductor substrate of the isolation region.

4. The method according to claim 1 , wherein:

an isolation trench is formed at the isolation region by removing the semiconductor substrate.

5. The method according to claim 4 , wherein:

a remaining top face of the conductor after removing the top portion of the conductor is at the same level as a bottom face of the isolation trench.

6. The method according to claim 4 , wherein:

the isolation trench is filled with the protective insulating film at the same time when the protective insulating film is formed on the conductor.

7. The method according to claim 6 , further comprising:

after forming the protective insulating film, a top face of the protective insulating film is flattened by CMP process,

wherein the protective insulating film is remained in the trench and the isolation trench.

8. The method according to claim 1 , wherein:

the conductor is polysilicon containing an impurity.

9. The method according to claim 1 , further comprising:

exposing the top face of the semiconductor substrate at an active region of the semiconductor device after forming the protective insulating film;

forming a gate insulating film on the active region;

forming a gate electrode facing the top face of the semiconductor substrate with an intervention of the gate insulating film therebetween;

forming a diffusion layer in the active region which is not covered by the gate electrode; and

forming an interlayer insulating film over the semiconductor substrate.

10. The method according to claim 9 , further comprising: the semiconductor substrate is ground from a rear face of the semiconductor substrate after forming the interlayer insulating film.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2014
From: ELPIDA MEMORY, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032645/0422 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 19, 2007
From: UCHIYAMA, SHIRO
To: ELPIDA MEMORY, INC.
Reel/Frame 019845/0460 →