Insulated-gate semiconductor device
View Patent ↗Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in polysilicon with a stripe shape below the gate pad electrode.
1. An insulated-gate semiconductor device comprising:
a semiconductor substrate of a first general conductivity type;
a plurality of gate electrodes formed on or in a surface portion of the semiconductor substrate in a form of stripes running in a first direction;
a plurality of channel regions of a second general conductivity type formed in the surface portion in a form of stripes running in the first direction;
a first insulating film formed between one of the plurality of gate electrodes and a corresponding one of the plurality of channel regions;
a plurality of source regions of the first general conductivity type formed in the plurality of channel regions in a form of stripes running in the first direction;
a gate pad electrode formed on the surface portion;
a plurality of pn junction diodes formed on or in the surface portion so as to be under the gate pad electrode and extend in the first direction, each of the plurality of pn junction diodes comprising a plurality of pn junctions serially connected;
a second insulating film formed on each of the plurality of gate electrodes, on the plurality of pn junction diodes and on portions of the plurality of channel regions, and
a source electrode formed on the surface portion so that the source electrode is disposed on the plurality of source regions and is electrically in contact with the plurality of source regions through contact holes formed in the second insulating film,
wherein the gate pad electrode is disposed on portions of a set of the plurality of channel regions so that other portions of the set of the plurality of channel regions extend from under the gate pad electrode and the source electrode is physically in contact with the other portions of the set of the plurality of channel regions extending from under the gate pad electrode, the plurality of channel regions in the set being continuous under the gate pad electrode.
2. The insulated-gate semiconductor device of claim 1 , further comprising a gate leading electrode formed on a peripheral portion of the semiconductor substrate and extending from the gate pad electrode so as to be electrically connected to the plurality of gate electrodes, and a high concentration region of the second general conductivity type formed in the surface portion under the gate leading electrode so as to be electrically connected to the plurality of channel regions.
3. The insulated-gate semiconductor device of claim 1 , wherein the portions of the plurality of channel regions under the gate pad electrode are electrically connected to the source electrode.
4. The insulated-gate semiconductor device of claim 1 , wherein each of the plurality of pn junction diodes is configured to receive at one end thereof a potential that is applied to the plurality of gate electrodes and to receive at another end thereof a potential that is applied to the plurality of source regions.
5. The insulated-gate semiconductor device of claim 1 , wherein the plurality of pn junction diodes are connected to each other in parallel to form a protection device connected between one of the plurality of gate electrode and the source electrode.
6. The insulated-gate semiconductor device of claim 1 , wherein a width of the plurality of pn junction diodes is equal to a width of the plurality of gate electrodes.
7. The insulated-gate semiconductor device of claim 1 , wherein none of the plurality of source regions are formed in the portions of the plurality of channel regions disposed under the gate pad electrode.
8. The insulated-gate semiconductor device of claim 1 , wherein the plurality of pn junction diodes are formed in a form of stripes running in the first direction, and the plurality of pn junctions of the plurality of pn junction diodes run perpendicular to the first direction.