Integrated circuits and methods of design and manufacture thereof
Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.
1. A method of manufacturing a semiconductor device, the method comprising:
depositing a conductive material over a semiconductor substrate, the conductive material covering a first and a second region;
using a first mask to pattern the conductive material, thereby forming a plurality of first and second features on the first region and a plurality of first and second features on the second region, wherein the first features comprise active components of the semiconductor device and the second features comprise dummy features; and
using a second mask to remove at least some of the second features from the first region and but not from the second region.
2. The method of claim 1 , wherein the first region comprises an isolated transistor region and the second region comprises a densely packed transistor region.
3. The method of claim 1 , wherein the first region and the second region each comprise an isolated transistor region.
4. The method of claim 1 , wherein the first region and the second region each comprise a densely packed transistor region.
5. A method of manufacturing a semiconductor device, the method comprising:
depositing a gate material over a semiconductor substrate;
using a first mask to pattern the gate material thereby forming a plurality of first and second features over the semiconductor substrate, wherein the first features comprise gate electrodes of the semiconductor device and the second features comprise dummy electrodes; and
using a second mask to remove selected ones of the plurality of second features, wherein the selected ones are based on a criterion that depends on a location of each second feature relative to at least one of the first features.
6. The method of claim 5 , wherein each gate electrode comprises a gate electrode of an isolated transistor.
7. The method of claim 5 , wherein using the second mask to remove selected ones of the plurality of second features comprises removing second features neighboring first features.
8. The method of claim 5 , wherein using the second mask to remove selected ones of the plurality of second features comprises removing first and second nearest neighbors to the first features.
9. The method of claim 5 , wherein using the second mask to remove selected ones of the plurality of second features creates an asymmetric semiconductor device.
10. The method of claim 5 , wherein the criterion for removing the selected ones of the plurality of second features comprises improving electrical performance of the semiconductor device.
11. The method of claim 5 , wherein the criterion for removing the selected ones of the plurality of second features comprises improving electrical performance of the semiconductor device without increasing layout area.
12. The method of claim 5 , wherein the criterion for removing the selected ones of the plurality of second features comprises improving electrical performance of the semiconductor device without decreasing process yield.
13. A method of manufacturing a semiconductor device, the method comprising:
forming isolation regions adjacent to active regions on a semiconductor substrate;
depositing a conductive material over the semiconductor substrate;
using a first mask to pattern the conductive material, thereby forming a plurality of features on the semiconductor substrate, wherein the features comprise conductive lines over the active regions and the isolation regions; and
using a second mask to remove some but not all of the conductive lines from over the isolation regions.
14. The method of claim 13 , wherein the conductive lines over the active regions comprise gate electrodes of isolated transistors.
15. The method of claim 13 , wherein using the second mask comprises removing the features neighboring the active regions.
16. The method of claim 13 , wherein using the second mask comprises removing first and second nearest neighbor features from the active regions.
17. The method of claim 13 , wherein using the second mask comprises forming an asymmetric semiconductor device.