IP Library Granted Patent US 7,582,512
Granted Patent B2
US 7,582,512 · App. 11/860,970 · Granted Sep 1, 2009

Method of fabricating semiconductor device having conducting portion of upper and lower conductive layers on a peripheral surface of the semiconductor device

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Quick Facts
Patent No.
US 7,582,512
App. No.
11/860,970
Granted
Sep 1, 2009
Kind
B2
Abstract

A semiconductor device includes a base plate, at least one first conductive layer carried by the base plate, and a semiconductor constructing body formed on or above the base plate, and having a semiconductor substrate and a plurality of external connecting electrodes formed on the semiconductor substrate. An insulating layer is formed on the base plate around the semiconductor constructing body. A plurality of second conductive layers are formed on the insulating layer and electrically connected to the external connecting electrodes of the semiconductor constructing body. A vertical conducting portion is formed on side surfaces of the insulating film and base plate, and electrically connects the first conductive layer and at least one of the second conductive layers.

Claims (20)

1. A semiconductor device fabrication method comprising:

arranging, on one side of a base plate carrying at least one first conductive layer, a plurality of semiconductor constructing bodies each having a semiconductor substrate and a plurality of external connecting electrodes formed on the semiconductor substrate, such that said plurality of semiconductor constructing bodies are spaced apart from each other;

forming an insulating layer on said one side of the base plate around each semiconductor constructing body;

forming a plurality of second conductive layers each having at least one layer on the semiconductor constructing body and insulating layer, such that said plurality of second conductive layers are electrically connected to the external connecting terminals of the semiconductor constructing body;

defining a cut line on the insulating layer of the base plate, the cut line defining a region such that at least one semiconductor constructing body is included in the region;

forming a vertical conducting portion which includes the cut line to extend to the cut line, and electrically connects the first conductive layer and at least one of the second conductive layers; and

cutting the insulating layer, base plate, and vertical conducting portion along the cut line, thereby obtaining a plurality of semiconductor devices each having a portion of the vertical conducting portion on a side surface.

2. The method according to claim 1 , wherein forming the vertical conducting portion comprises forming a through hole which extends through the insulating layer and base plate, and forming a vertical conducting layer in the through hole.

3. The method according to claim 2 , wherein forming the through hole comprises irradiating the insulating layer and base plate with a laser beam.

4. The method according to claim 1 , wherein arranging the semiconductor constructing bodies on the base plate comprises forming a conductive adhesive layer on the base plate, and adhering the semiconductor substrate of each semiconductor constructing body to the conductive adhesive layer.

5. A semiconductor device fabrication method comprising:

arranging, on one side of a base plate carrying a plurality of semiconductor constructing bodies each having a semiconductor substrate and a plurality of external connecting electrodes formed on the semiconductor substrate, such that said plurality of semiconductor constructing bodies are spaced apart from each other;

forming an insulating layer on said one side of the base plate around each semiconductor constructing body;

forming a plurality of second conductive layers each having at least one layer on the semiconductor constructing body and insulating layer, such that said plurality of second conductive layers are electrically connected to the external connecting electrodes of the semiconductor constructing body;

forming at least one first conductive layer on a bottom surface of the base plate;

defining a cut line on the insulating layer of the base plate, the cut line defining a region such that at least one semiconductor constructing body is included in the region;

forming a vertical conducting portion which includes the cut line to extend to the cut line, and electrically connects the first conductive layer and at least one of the second conductive layers; and

cutting the insulating layer, base plate, and vertical conducting portion along the cut line, thereby obtaining a plurality of semiconductor devices each having a portion of the vertical conducting portion on a side surface.

6. The method according to claim 5 , wherein forming the vertical conducting portion comprises forming a through hole which extends through the insulating layer and base plate, and forming a vertical conducting layer in the through hole.

7. The method according to claim 6 , wherein forming the through hole comprises irradiating the insulating layer and base plate with a laser beam.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2017
From: TERA PROBE, INC.
To: AOI ELECTRONICS CO., LTD.
Reel/Frame 041521/0001 →
MERGER Recorded Jan 27, 2017
From: TERAMIKROS, INC.
To: TERA PROBE, INC.
Reel/Frame 041664/0471 →
CHANGE OF OWNERSHIP BY CORPORATE SEPARATION-TO CORRECT ASSIGNEE'S ADDRESS ON REEL 027465, FRAME 0812 Recorded Jan 6, 2012
From: CASIO COMPUTER CO., LTD.
To: TERAMIKROS, INC.
Reel/Frame 027492/0449 →
CHANGE OF OWNERSHIP BY CORPORATE SEPARATION Recorded Jan 3, 2012
From: CASIO COMPUTER CO., LTD.
To: TERAMIKROS, INC.
Reel/Frame 027465/0812 →