Semiconductor device
View Patent ↗A transistor structure that improves an ESD withstand voltage is offered. There is formed a P-type insulating isolation layer that divides an N-type epitaxial layer into a plurality of regions and isolates neighboring regions from each other. A diffusion layer doped with high concentration N-type impurities and an electrode extraction layer are formed in a surface of the epitaxial layer between a low impurity concentration drain layer and the insulating isolation layer. The diffusion layer and the electrode extraction layer are connected with a drain electrode. When an excessive positive surge voltage is applied to a source electrode, a parasitic diode that makes a current path including the diffusion layer and the electrode extraction layer is turned on to shunt an ESD current from the source electrode to the drain electrode, in addition to other parasitic diodes included in a conventional structure.
1. A semiconductor device comprising:
a semiconductor substrate of a first general conductivity type;
a semiconductor layer of a second general conductivity type formed on the semiconductor substrate;
a body layer of the first general conductivity type formed in a surface portion of the semiconductor layer, the body layer comprising a channel region;
a source layer of the second general conductivity type formed in a surface portion of the body layer;
a gate electrode disposed on a portion of the body layer;
a gate insulation film disposed between the channel region and the gate electrode;
a drain layer of the second general conductivity type formed in the surface portion of the semiconductor layer;
an insulating isolation layer of the first general conductivity type that isolates a region of the semiconductor layer in which the body layer is formed from other region of the semiconductor layer;
a drain electrode electrically connected to the drain layer; and
a diffusion layer of the second general conductivity type electrically connected to the drain electrode and physically separated from the drain layer,
wherein the drain layer is disposed between the source layer and the diffusion layer.
2. The semiconductor device of claim 1 , further comprising a buried layer of the second general conductivity type formed at an interface between the semiconductor substrate and the semiconductor layer, wherein the diffusion layer is physically in contact with the buried layer.
3. The semiconductor device of claim 1 , further comprising a source electrode, wherein the source electrode is electrically connected to the semiconductor substrate.
4. The semiconductor device of claim 1 , wherein the diffusion layer is disposed between the body layer and the insulating isolation layer so as to surround the body layer.
5. The semiconductor device of claim 1 , further comprising an electric potential fixing layer of the first general conductivity type formed in the body layer and is adjacent the source layer, wherein the diffusion layer is disposed between the electric potential fixing layer and the insulating isolation layer.
6. The semiconductor device of claim 1 , further comprising a thick insulation film that is thicker than the gate insulation film and disposed on the semiconductor layer, wherein the gate electrode extends over a portion of the thick insulation film.
7. The semiconductor device of claim 1 , wherein in plan view of the semiconductor device the drain layer and the diffusion layer do not overlap.