Semiconductor device with constricted current passage
View Patent ↗A semiconductor device including a gate located over a semiconductor substrate and a source/drain region located adjacent the gate. The source/drain region is bounded by an isolation structure that includes a constricted current passage between the gate and the source/drain region.
1. A method of manufacturing a semiconductor device, comprising:
forming a gate over a semiconductor substrate;
forming a source/drain region in said semiconductor substrate, said source/drain region located adjacent said gate; and
forming an isolation structure in said semiconductor substrate, said isolation structure forming a continuous boundary around said source/drain region except for a constricted current passage in said continuous boundary, said constricted current passage located between said gate and said source/drain region.
2. The method of manufacturing a semiconductor device as recited in claim 1 wherein said isolation structure has a serpentine contour.
3. The method of manufacturing a semiconductor device as recited in claim 1 wherein said forming said isolation structure includes forming a mask over said semiconductor substrate and implanting dopant into said semiconductor substrate around said mask to form said source/drain region.
4. The method of manufacturing a semiconductor device as recited in claim 3 wherein said forming said mask occurs simultaneously with said forming said gate.
5. The method of manufacturing a semiconductor device as recited in claim 1 wherein said forming said isolation structure includes forming a portion of said semiconductor substrate having decreased conductivity relative to said source/drain region.
6. The method of manufacturing a semiconductor device as recited in claim 1 wherein said forming said isolation structure includes forming a shallow trench isolation in said semiconductor substrate.
7. The method of manufacturing a semiconductor device as recited in claim 1 wherein said forming said gate includes forming first and second gates separated by a region comprising said isolation structure and said source/drain region.
8. The method of manufacturing a semiconductor device as recited in claim 1 wherein said semiconductor substrate is doped with a first dopant type and said forming said source/drain region includes implanting a second dopant type that is opposite said first dopant type.