IP Library Granted Patent US 7,700,456
Granted Patent B2
US 7,700,456 · App. 11/872,794 · Granted Apr 20, 2010

Semiconductor device and manufacturing method of the same

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Quick Facts
Patent No.
US 7,700,456
App. No.
11/872,794
Granted
Apr 20, 2010
Kind
B2
Abstract

A manufacturing method of a semiconductor device includes a step of defining an element region by etching a semiconductor substrate using a first dielectric film as a mask, a step of reducing the first dielectric film by isotropic etching, a step of forming a side wall on a side surface of the reduced first dielectric film, a step of removing the first dielectric film, and a step of forming a trench in the element region by etching using the side wall as a mask to form a plurality of fin portions at the element region.

Claims (30)

1. A method for manufacturing a semiconductor device, comprising:

defining an element region by etching a semiconductor substrate using a first dielectric film as a mask;

reducing the first dielectric film to form a reduced dielectric film;

covering the reduced dielectric film with a second dielectric film different from the first dielectric film, the second dielectric film including a first portion over an upper surface of the reduced dielectric film and a second portion surrounding a side surface of the reduced dielectric film;

etching back the second dielectric film to remove the first portion and leave the second portion;

removing the reduced dielectric film while leaving the second portion; and

forming a trench in the element region by using the second portion as a mask to form a plurality of fin portions.

2. The method claimed in claim 1 , further comprising:

embedding the element region with a third dielectric film after the defining step;

planarizing the third dielectric film; and

aligning a surface of the third dielectric film with a surface of the element region.

3. The method claimed in claim 2 , further comprising:

removing the second portion; and

aligning the surface of the third dielectric film with a bottom of the trench.

4. A method for manufacturing a semiconductor device, comprising:

defining an element region by etching a semiconductor substrate using a first dielectric film as a mask;

reducing the first dielectric film to form a reduced dielectric film;

covering the reduced dielectric film with a second dielectric film different from the first dielectric film, the second dielectric film including a first portion over an upper surface of the reduced dielectric film and a second portion surrounding a side surface of the reduced dielectric film;

etching back the second dielectric film to remove the first portion and leave the second portion;

removing the reduced dielectric film while leaving the second portion;

forming a trench in the element region by using the second portion as a mask to form a plurality of fin portions;

the trench including a center portion and third and fourth portions sandwiching the center portion therebetween; and

filling a gate electrode in the center portion of the trench while leaving each of the third and fourth portions of the trench unfilled with the gate electrode.

5. The method claimed in claim 4 , further comprising:

embedding the element region with a third dielectric film after the defining;

planarizing the third dielectric film; and

aligning a surface of the third dielectric film with a surface of the element region.

6. The method claimed in claim 5 , further comprising:

removing the second portion; and

aligning the surface of the third dielectric film with a bottom of the trench.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2014
From: ELPIDA MEMORY, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032645/0422 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 16, 2007
From: MIKASA, NORIAKI
To: ELPIDA MEMORY, INC.
Reel/Frame 019967/0538 →