Split charge storage node inner spacer process
View Patent ↗Methods of forming a memory cell containing two split sub-lithographic charge storage nodes on a semiconductor substrate are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing exposed portions of a first poly layer while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing exposed portions of a charge storage layer while leaving portions of the charge storage layer protected by the two split sub-lithographic first poly gates, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.
1. A method of making a memory cell comprising two split sub-lithographic charge storage nodes, comprising:
providing a charge storage layer, a first poly layer, and a first mask layer on a semiconductor substrate;
patterning the first mask layer;
forming spacers adjacent side surfaces of the patterned first mask layer and on portions of the upper surface of the first poly layer;
removing exposed portions of the first poly layer that are not covered with the patterned first mask layer and spacers, thereby forming first openings;
forming a second mask layer at the first openings;
removing the patterned first mask layer, thereby exposing portions of the patterned first poly layer;
removing the exposed portions of the patterned first poly layer, thereby exposing portions of the charge storage layer and forming two sub-lithographic first poly gates;
removing the exposed portions of the charge storage layer, thereby forming second openings;
forming a third oxide layer on the spacers and second mask layer and in the second openings;
removing portions of the third oxide layer on the spacers and second mask layer, thereby exposing upper portions of the spacers and second mask layer;
removing the spacers and second mask layer, thereby exposing portions of the charge storage layer at the bottom of the first opening;
removing at least a portion of exposed portions of the charge storage layer at the bottom of the first opening, thereby forming two split sub-lithographic charge storage nodes between the sub-lithographic first poly gates and the semiconductor substrate, and forming bit line openings;
implanting portions of the semiconductor substrate through the bit line openings;
forming fourth oxides in the bit line openings; and
forming a third poly gate over the semiconductor substrate.
2. The method of claim 1 , wherein forming the third oxide layer comprises a high temperature oxide deposition process and forming the fourth oxides comprises a high density plasma oxide deposition process.
3. The method of claim 1 , wherein forming bit line openings comprises removing substantially all of the exposed portions of the charge storage layer at the bottom of the first opening.
4. The method of claim 1 , wherein while forming the second opening, upper portions of the spacer and second mask layer are removed.
5. The method of claim 1 further comprising forming a second poly gate between the two split sub-lithographic charge storage nodes on the semiconductor substrate.
6. The method of claim 1 , wherein the spacer has a length of about 5 nm or more and about 50 nm or less.
7. The method of claim 1 , wherein the sub-lithographic charge storage node has a length of about 5 nm or more and about 50 nm or less.
8. The method of claim 1 , wherein the sub-lithographic charge storage node has a length of about 10 nm or more and about 40 nm or less.
9. The method of claim 1 , wherein the sub-lithographic charge storage node has a length of about 15 nm or more and about 35 nm or less.
10. The method of claim 1 , wherein the charge storage layer comprises a first oxide layer, nitride layer, and second oxide layer.
11. The method of claim 1 , wherein forming the third oxide layer comprises a high temperature oxide deposition process.
12. The method of claim 1 , wherein forming the third oxide layer comprises a plasma oxide deposition process.
13. The method of claim 1 , wherein forming the third oxide layer comprises a slot plane antenna process.
14. The method of claim 1 , wherein forming the fourth oxide comprises a high temperature oxide deposition process.
15. The method of claim 1 , wherein forming the fourth oxide comprises a plasma oxide deposition process.
16. The method of claim 1 , wherein forming the fourth oxide comprises a slot plane antenna process.