Wrapped gate junction field effect transistor
View Patent ↗A wrapped gate junction field effect transistor (JFET) with at least one semiconductor channel having a first conductivity type doping is provided. Both sidewalls of each of the at least one semiconductor channel laterally abuts a side gate region having a second conductivity type doping, which is the opposite of the first conductivity doping. Further, the at least one semiconductor channel vertically abuts a top gate region and at least one bottom gate region, both having the second conductivity type doping. The gate electrode, which comprises side gate region, the top gate region, and at least one bottom gate regions, wraps around each of the at least one semiconductor channel to provide tight control of the current, i.e., a low off-current, through the at least one semiconductor channel. By employing multiple channels, the JFET may provide a high on-current.
1. A semiconductor structure comprising:
at least one semiconductor channel having a first conductivity type doping and located in a semiconductor substrate;
a gate electrode containing:
a side gate region laterally abutting said at least one semiconductor channel and having a second conductivity type doping, wherein said second conductivity type is the opposite of said first conductivity type;
a top gate region vertically abutting said at least one semiconductor channel and having said second conductivity type doping; and
at least one bottom gate region vertically abutting said at least one semiconductor channel and having said second conductivity type doping;
a shallow trench isolation structure including a dielectric material and laterally surrounding said top gate region;
a buried doped layer vertically abutting said at least one bottom gate region and having a doping of said first conductivity type; and
a substrate layer located in said semiconductor substrate, vertically abutting said buried doped layer and having a doping of said second conductivity type.
2. The semiconductor structure of claim 1 , further comprising:
a source region having said first conductivity type doping and abutting a first end portion of each of said at least one semiconductor channel; and
a drain region having said first conductivity type doping and abutting a second end portion of each of said at least one semiconductor channel, wherein said second end portion is located on the opposite side of said first end portion in each of said at least one semiconductor channel.
3. The semiconductor structure of claim 2 , wherein said shallow trench isolation structure is located between said top gate region and said source region and between said top gate region and said drain region.
4. The semiconductor structure of claim 3 , wherein said top gate region, said source region, said drain region, said shallow trench isolation, said side gate region, and said at least one bottom gate region encapsulates each of said at least one semiconductor channel.
5. The semiconductor structure of claim 2 , further comprising a dielectric layer abutting said at least one semiconductor channel and located between said top gate region and said source region and between said top gate region and said drain region.
6. The semiconductor structure of claim 5 , wherein said top gate region, said source region, said drain region, said dielectric layer, said side gate region, and said at least one bottom gate region encapsulates each of said at least one semiconductor channel.
7. The semiconductor structure of claim 2 , wherein said source region and said drain region have a doping concentration from about 3.0×10 19 /cm 3 to about 3.0×10 21 /cm 3 in atomic concentration.
8. A semiconductor structure comprising:
at least one semiconductor channel having a first conductivity type doping and located in a semiconductor substrate;
a gate electrode containing:
a side gate region laterally abutting said at least one semiconductor channel and having a second conductivity type doping, wherein said second conductivity type is the opposite of said first conductivity type,
a top gate region vertically abutting said at least one semiconductor channel and having said second conductivity type doping, and
at least one bottom gate region vertically abutting said at least one semiconductor channel and having said second conductivity type doping;
a first conductivity type well laterally abutting and surrounding said side gate region;
a first conductivity type buried doped layer vertically abutting said side gate region; and
a second conductivity type substrate layer vertically abutting said first conductivity type buried doped layer, wherein said first conductivity type buried doped layer and said first conductivity type well separates said second conductivity type substrate layer from said side gate region.
9. The semiconductor structure of claim 1 , further comprising a first conductivity type substrate layer surrounding and vertically abutting said side gate region.
10. The semiconductor structure of claim 1 , further comprising:
a buried insulator layer vertically abutting said side gate region; and
a handle substrate vertically abutting said buried insulator layer.
11. The semiconductor structure of claim 1 , wherein said at least one semiconductor channel has a doping concentration from about 3.0×10 15 /cm 3 to about 3.0×10 19 /cm 3 , said side gate region has a doping concentration from about 3.0×10 16 /cm 3 to about 3.0×10 19 /cm 3 , said at least one bottom gate region has a doping concentration from about 3.0×10 16 /cm 3 to about 3.0×10 19 /cm 3 , and said top gate region has a doping concentration from about 3.0×10 16 /cm 3 to about 3.0×10 21 /cm 3 .
12. A semiconductor structure comprising:
at least one semiconductor channel having a first conductivity type doping and located in a semiconductor substrate;
a gate electrode containing:
a side gate region laterally abutting said at least one semiconductor channel and having a second conductivity type doping, wherein said second conductivity type is the opposite of said first conductivity type,
a top gate region vertically abutting said at least one semiconductor channel and having said second conductivity type doping, and
at least one bottom gate region vertically abutting said at least one semiconductor channel and having said second conductivity type doping,
wherein said at least one semiconductor channel is a plurality of semiconductor channels separated by portions of said side gate region amongst one another, and wherein said side gate region is of unitary construction and has a plurality of holes in which said plurality of semiconductor channels are located.
13. The semiconductor structure of claim 8 , further comprising:
a buried doped layer vertically abutting said at least one bottom gate region and having a doping of said first conductivity type; and
a substrate layer located in said semiconductor substrate, vertically abutting said buried doped layer and having a doping of said second conductivity type.
14. The semiconductor structure of claim 12 , further comprising:
a buried doped layer vertically abutting said at least one bottom gate region and having a doping of said first conductivity type; and
a substrate layer located in said semiconductor substrate, vertically abutting said buried doped layer and having a doping of said second conductivity type.