IP Library Granted Patent US 7,795,689
Granted Patent B2
US 7,795,689 · App. 11/878,294 · Granted Sep 14, 2010

Semiconductor device including a germanium silicide film on a selective epitaxial layer

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Quick Facts
Patent No.
US 7,795,689
App. No.
11/878,294
Granted
Sep 14, 2010
Kind
B2
Abstract

A process for manufacturing a semiconductor device includes: forming first contact holes in a dielectric film for a PMOS transistor; depositing germanium on the source/drain regions of the PMOS transistor exposed from the first contact holes; heat treating the germanium with silicon in the source/drain regions of the PMOS transistor to form a germanium silicide film; forming second contact holes in the dielectric film for the source/drain regions of the NMOS transistor; and forming contact plugs in the first and second contact holes.

Claims (52)

1. A semiconductor device comprising:

a silicon substrate;

a PMOS transistor formed on said silicon substrate and including a source/drain region and a contact layer formed on said source/drain region;

a dielectric film formed on said PMOS transistor and including therein a first contact hole penetrating said dielectric film, said contact layer, and a surface of said source/drain region of said PMOS transistor, the first contact hole having a bottom within the source/drain region;

a germanium silicide film formed in said first contact hole and having a side formed on said contact layer and a bottom formed at the bottom of the first contact hole and in contact with said source/drain region of said PMOS transistor; and

a first contact plug connecting to said germanium silicide film in said first contact hole.

2. The semiconductor device according to claim 1 , wherein said first contact hole has a bottom located below a gate oxide film of said PMOS transistor.

3. The semiconductor device according to claim 2 , further comprising:

an NMOS transistor formed on said silicon substrate; and

a second contact hole penetrating through said dielectric film to react a source/drain region of said NMOS transistor, said second contact hole having a bottom located above said bottom of said first contact hole.

4. The semiconductor device according to claim 3 , wherein said first contact hole has an elliptical shape in cross section.

5. The semiconductor device according to claim 4 , wherein said second contact hole has a circular shape in cross section.

6. The semiconductor device according to claim 3 , wherein said first contact hole includes a plurality of elliptical holes arranged in a direction of major axis of said elliptical holes.

7. The semiconductor device according to claim 1 , further comprising:

an NMOS transistor formed on said silicon substrate, said contact layer comprising an impurity-doped silicon film deposited by a selective epitaxial deposition process on said source/drain region of said PMOS transistor and a source/drain region of said NMOS transistor; and

a second contact plug formed in a second contact hole penetrating said dielectric film and connecting to said source/drain region of said NMOS transistor,

wherein said first contact hole penetrates said impurity-doped silicon layer to reach said source/drain region of said PMOS transistor.

8. The semiconductor device according to claim 7 , wherein said germanium silicide film is in contact with said impurity-doped silicon film on a sidewall of said first contact hole.

9. A method for manufacturing a semiconductor device comprising:

forming a PMOS transistor and an NMOS transistor each including a source/drain region and a contact layer formed on said source/drain region;

forming a dielectric film covering said PMOS transistor and said NMOS transistor,

forming a first contact hole penetrating said dielectric film, said contact layer, and a surface of said source/drain region of said PMOS transistor, the first contact hole having a bottom within the source/drain region;

depositing germanium on said source/drain region of said PMOS transistor at the bottom of said first contact hole;

heat treating said deposited germanium to react with silicon in said source/drain region of said PMOS transistor and thereby form a germanium silicide film in said first contact hole and having a side formed on said contact layer and a bottom in contact with said source/drain region of said PMOS transistor; and

forming a first contact plug connecting to said germanium silicide film within said first contact hole.

10. The method according to claim 9 , further comprising, prior to said forming said dielectric film:

forming said contact layer by selectively depositing an impurity-doped silicon film on said source/drain region of said PMOS transistor and said NMOS transistor.

11. The method according to claim 10 , further comprising:

after said heat treating, forming a second contact hole penetrating said dielectric film to reach said impurity-doped silicon film formed on said source/drain region of said NMOS transistor.

12. The method according to claim 11 , wherein said forming second contact hole also forms a gate contact hole exposing therethrough a gate electrode of said PMOS transistor and said NMOS transistor.

13. The method according to claim 11 , wherein said first contact hole has an elliptical shape and said second contact hole has a circular shape.

14. The method according to claim 13 , wherein said first contact hole includes a plurality of elliptical holes.

15. The semiconductor device according to claim 3 , wherein a cross-sectional shape of the first contact hole is different than a cross-sectional shape of the second contact hole.

16. The semiconductor device according to claim 3 , wherein the NMOS transistor comprises a contact layer formed on the source/drain region of the NMOS transistor, and

wherein the bottom of the second contact hole is defined by a surface of the contact layer.

17. The semiconductor device according to claim 16 , wherein the contact layer of the PMOS transistor comprises a P + diffused contact region and the contact layer of the NMOS transistor comprises an N + diffused contact region.

18. A semiconductor device comprising:

a transistor formed on a silicon substrate and including a source/drain region and a contact layer formed on the source/drain region;

a dielectric film formed on the transistor, a contact hole being formed in the dielectric film, the contact layer, and a surface of the source/drain region of the transistor, the contact hole having a bottom within the source/drain region;

a germanium silicide film formed in the contact hole and including a side formed on the contact layer and a bottom formed at the bottom of the contact hole and in contact with the source/drain region of the transistor; and

a contact plug formed in the contact hole and connected to the germanium silicide film in the contact hole.

19. A semiconductor device comprising:

a transistor formed on a silicon substrate and including a source/drain region;

a dielectric film formed on the transistor, a contact hole being formed in the dielectric film and having a bottom within the source/drain region;

a germanium silicide film formed on an inner sidewall of the contact hole and including a bottom formed at the bottom of the contact hole and in contact with the source/drain region; and

a contact plug formed in the contact hole and connected to the germanium silicide film in the contact hole.

20. A method of manufacturing a semiconductor device comprising:

forming a transistor including a source/drain region on a silicon substrate;

forming a dielectric film on the transistor;

forming a contact hole in the dielectric film, the contact hole having a bottom within the source/drain region;

forming a germanium silicide film on an inner sidewall of the contact hole, the germanium silicide film having a bottom formed at the bottom of the contact hole and in contact with the source/drain region; and

forming a contact plug in contact with the silicide film within the contact hole.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2014
From: ELPIDA MEMORY, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032645/0422 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 23, 2007
From: KAWAKITA, KEIZO
To: ELPIDA MEMORY, INC.
Reel/Frame 019653/0236 →