Nonvolatile storage and erase control

1. A nonvolatile storage which has a plurality of blocks each serving as one unit in an erasing operation, the nonvolatile storage comprising:

a volatile memory cell array for storing erase setting information on each block, the information indicating whether or not its associated block is a target to be erased;

a write amplifier for writing the erase setting information in the volatile memory cell array;

a first readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array according to an erasing operation; and

a second readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array according to a readout operation.

2. The nonvolatile storage according to claim 1 , wherein the erase setting information is stored in the volatile memory cell array prior to the erasing operation.

3. The nonvolatile storage according to claim 1 , wherein the readout operation is performed in a period when the erasing operation is performed.

4. The nonvolatile storage according to claim 1 , wherein the volatile memory cell array uses a block address for identifying each block as the storage address of the erase setting information associated with the block.

5. The nonvolatile storage according to claim 1 , further comprising:

a first data line for coupling the volatile memory cell array to the first readout amplifier; and

a second data line for coupling the volatile memory cell array to the second readout amplifier.

6. The nonvolatile storage according to claim 5 , wherein the write amplifier is coupled to the first or second data line.

7. The nonvolatile storage according to claim 5 ,

wherein the volatile memory cell array comprises:

first select gates each of which is selected according to a block address that designates a target block of the erasing operation and each of which is for coupling a memory cell to the first data line; and

second select gates each of which is selected according to a block address that designates a target block of the readout operation and each of which is for coupling a memory cell to the second data line.

8. The nonvolatile storage according to claim 7 , further comprising:

a match detection unit for detecting a match between a block address that designates a target block of the erasing operation and a block address that designates a target block of the readout operation when the erasing operation and the readout operation are respectively performed with an independent timing;

a select gate control unit for un-selecting either the first or second select gates selected according to a block address, according to the result of the match detection performed by the match detection unit; and

an amplifier output control unit for outputting an output signal from either the first or second readout amplifier coupled to the first or second select gate maintained in a selected state according to the result of the match detection performed by the match detection unit.

9. An erase control method for a nonvolatile storage which has a plurality of blocks each serving as one unit in an erasing operation, the method comprising:

storing erase setting information on each block in a volatile memory cell array, the erase setting information indicating whether or not its associated block is a target to be erased;

reading out the erase setting information on a target block among the stored erase setting information through a first path upon start of an erasing operation; and

reading out the erase setting information on a target block among the stored erase setting information through a second path upon start of a readout operation.

10. The erase control method for a nonvolatile storage according to claim 9 , wherein the readout operation is performed in a period when the erasing operation is performed.

11. The erase control method for a nonvolatile storage according to claim 9 , wherein the storing erase setting information comprises a block address for designating each block is used as the storage address of the erase setting information associated with the block.

12. The erase control method for a nonvolatile storage according to claim 9 , wherein the storing erase setting information comprises the erase setting information is stored through either the first or second path.

13. The erase control method for a nonvolatile storage according to claim 9 , the method further comprising:

detecting a match between a block address that designates a target block of the erasing operation and a block address that designates a target block of the readout operation when the erasing operation and the readout operation are respectively performed with an independent timing;

un-selecting either the first or second path selected according to the block address, according to the result of the match detection performed in the detecting the match; and

determining the erase setting information read out from either the first or second path maintained in a selected state to be erase setting information for the erasing operation and the readout operation according to the result of the match detection performed in the detecting the match.

14. A wireless communications device, comprising:

a processor;

a communications component coupled to the processor;

a transmitter coupled to the processor;

a receiver;

an antenna coupled to the transmitter circuit and the receiver circuit; and

a memory coupled to the processor, the memory including a plurality of blocks each serving as one unit in an erasing operation, the memory comprising:

a volatile memory cell array for storing erase setting information on each block, the information indicating whether or not its associated block is a target to be erased;

a write amplifier for writing the erase setting information in the volatile memory cell array;

a first readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array according to an erasing operation; and

a second readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array according to a readout operation.

15. The wireless communications device of claim 14 , wherein said flash memory is NAND flash memory.

16. The wireless communications device of claim 14 , wherein said flash memory is NOR flash memory.

17. The wireless communications device of claim 14 , wherein said flash memory comprises at least one memory cell operable to store more than one bit.

18. A computing device comprising:

a processor;

an input component coupled to the processor;

an output component coupled to the processor; and

a memory coupled to the processor, the memory including a plurality of blocks each serving as one unit in an erasing operation, the memory comprising:

a volatile memory cell array for storing erase setting information on each block, the information indicating whether or not its associated block is a target to be erased;

a write amplifier for writing the erase setting information in the volatile memory cell array;

a first readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array according to an erasing operation; and

a second readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array according to a readout operation.

19. The computing device of claim 18 , wherein said computing device is a personal computer (PC).

20. The computing device of claim 18 , wherein said computing device is a personal digital assistant (PDA).

21. The computing device of claim 18 , wherein said computing device is a gaming system.

22. A portable media player comprising:

a processor;

a cache coupled to the processor;

a user input component coupled to the processor;

a coder-decoder component coupled to the processor; and

a memory coupled to the processor, the memory including a plurality of blocks each serving as one unit in an erasing operation, the memory comprising:

a volatile memory cell array for storing erase setting information on each block, the information indicating whether or not its associated block is a target to be erased;

a write amplifier for writing the erase setting information in the volatile memory cell array;

a first readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array according to an erasing operation; and

a second readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array according to a readout operation.

23. The portable media player of claim 22 , wherein said portable media player is a portable music player.

24. The portable media player of claim 22 , wherein said portable media player is a portable video player.