Patent Assignment
Reel/Frame 030945/0505
RELEASE OF LIEN ON PATENT
Recorded: 2013-08-05
Received: 2013-08-05
Pages: 16
Assignor
BARCLAYS BANK PLC
Executed: 2013-08-05
Assignees
SPANSION LLC
915 DEGUIGNE DRIVE, SUNNYVALE, CA, 94088, UNITED STATES
SPANSION INC.
915 DEGUIGNE DRIVE, SUNNYVALE, CA, 94088, UNITED STATES
SPANSION TECHNOLOGY INC.
915 DEGUIGNE DRIVE, SUNNYVALE, CA, 94088, UNITED STATES
SPANSION TECHNOLOGY LLC
915 DEGUIGNE DRIVE, SUNNYVALE, CA, 94088, UNITED STATES
Covered Applications
(39)
SEMICONDUCTOR DEVICE WITH SEALING RESIN
App. No. 13/711,443
→
METHODS OF MAKING A SEMICONDUCTOR DEVICE
App. No. 12/965,706
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SEMICONDUCTOR DEVICE
App. No. 12/965,672
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SEMICONDUCTOR DEVICE
App. No. 12/624,117
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READING ELECTRONIC MEMORY UTILIZING RELATIONSHIPS BETWEEN CELL STATE DISTRIBUTIONS
App. No. 12/550,642
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SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREOF
App. No. 12/433,084
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APPLYING NEGATIVE GATE VOLTAGE TO WORDLINES ADJACENT TO WORDLINE ASSOCIATED WITH READ OR VERIFY TO REDUCE ADJACENT WORDLINE DISTURB
App. No. 12/275,663
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IMPLEMENTATION OF RECYCLING UNUSED ECC PARITY BITS DURING FLASH MEMORY PROGRAMMING
App. No. 12/198,381
→
TRANSLATION TABLE COHERENCY MECAHANISM USING CACHE WAY AND SET INDEX WRITE BUFFERS
App. No. 12/020,698
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TRANSLATION MANAGEMENT OF LOGICAL BLOCK ADDRESSES AND PHYSICAL BLOCK ADDRESSES
App. No. 11/966,919
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BIT MAP CONTROL OF ERASE BLOCK DEFECT LIST IN A MEMORY
App. No. 11/963,286
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PHYSICAL BLOCK ADDRESSING OF ELECTRONIC MEMORY DEVICES
App. No. 11/963,306
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COMMAND QUEUING FOR NEXT OPERATIONS OF MEMORY DEVICES
App. No. 11/962,918
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ADAPTIVE SYSTEM BOOT ACCELERATOR FOR COMPUTING SYSTEMS
App. No. 11/957,793
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READING ELECTRONIC MEMORY UTILIZING RELATIONSHIPS BETWEEN CELL STATE DISTRIBUTIONS
App. No. 11/957,309
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POWER SAFE TRANSLATION TABLE OPERATION IN FLASH MEMORY
App. No. 11/955,934
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MEMORY ARRAY SEARCH ENGINE
App. No. 11/953,501
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ADDRESS/DATA MULTIPLEXED DEVICE
App. No. 11/986,385
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MEMORY DEVICE AND PASSWORD STORING METHOD THEREOF
App. No. 11/986,332
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CONTROLLING A SEMICONDUCTOR DEVICE
App. No. 11/982,864
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DETERMINISTIC PROGRAMMING ALGORITHM THAT PROVIDES TIGHTER CELL DISTRIBUTIONS WITH A REDUCED NUMBER OF PROGRAMMING PULSES
App. No. 11/929,741
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TAMPER REACTIVE MEMORY DEVICE TO SECURE DATA FROM TAMPER ATTACKS
App. No. 11/873,980
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NONVOLATILE STORAGE AND ERASE CONTROL
App. No. 11/879,989
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MANAGING FLASH MEMORY BASED UPON USAGE HISTORY
App. No. 11/747,608
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SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
App. No. 11/654,704
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SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREFOR
App. No. 11/543,399
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COMPUTING DEVICE INCLUDING A STACKED SEMICONDUCTOR DEVICE
App. No. 11/514,390
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SEMICONDUCTOR DEVICE AND PROGRAM DATA REDUNDANCY METHOD THEREFOR
App. No. 11/444,251
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SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME
App. No. 11/394,491
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PROGRAM AND PROGRAM VERIFY OPERATIONS FOR FLASH MEMORY
App. No. 11/332,263
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SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING SAID SEMICONDUCTOR DEVICE
App. No. 11/290,002
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SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE TESTING METHOD, AND PROGRAMMING METHOD
App. No. 11/215,253
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MEMORY DEVICE INCLUDING BARRIER LAYER FOR IMPROVED SWITCHING SPEED AND DATA RETENTION
App. No. 11/052,689
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METHOD OF PROGRAMMING A FLASH MEMORY DEVICE USING MULTILEVEL CHARGE STORAGE
App. No. 10/896,651
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MINIMIZATION OF FG-FG COUPLING IN FLASH MEMORY
App. No. 10/700,414
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MEMORY DEVICE FOR CONTROLLING NONVOLATILE AND VOLATILE MEMORIES
App. No. 10/077,778
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DOUBLE BOOSTING SCHEME FOR NAND TO IMPROVE PROGRAM INHIBIT CHARACTERISTICS
App. No. 09/922,415
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Descending staircase read technique for a multilevel cell NAND flash memory device
App. No. 09/794,485
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ADDRESS BROADCASTING TO A PAGED MEMORY DEVICE TO ELIMINATE ACCESS LATENCY PENALTY
App. No. 09/794,478
→