Memory device including barrier layer for improved switching speed and data retention
View Patent ↗The present memory device includes a first electrode, a passive layer on and in contact with the first electrode, the passive layer including copper sulfide, a barrier layer on and in contact with the passive layer, an active layer on and in contact with the barrier layer, and a second electrode on and in contact with the active layer. The inclusion of the barrier layer in this environment increases switching speed of the memory device, while also improving data retention thereof.
1. A memory device comprising:
a first electrode;
a passive layer on and in contact with the first electrode, the passive layer comprising copper sulfide;
a barrier layer on and in contact with the passive layer;
an active layer on and in contact with the barrier layer; and
a second electrode on and in contact with the active layer;
wherein the barrier layer comprises at least one material selected from the group consisting of CuO x , WO x , NiO x , and TiO x .
2. The memory device of claim 1 wherein the first electrode comprises copper.
3. The memory device of claim 1 wherein the active layer is an organic layer.
4. The memory device of claim 1 wherein the active layer is an inorganic layer.
5. A memory device comprising:
a first electrode;
a passive layer on and in contact with the first electrode;
a barrier layer on and in contact with the passive layer, wherein the barrier layer comprises at least one material selected from the group consisting of CuO x , WO x , NiO x , and TiO x ,
an active layer on and in contact with the barrier layer; and
a second electrode on and in contact with the active layer.
6. The memory device of claim 5 wherein the passive layer is copper sulfide.
7. The memory device of claim 6 wherein the first electrode is copper.
8. The memory device of claim 7 wherein the active layer is an organic layer.
9. The memory device of claim 7 wherein the active layer is an inorganic layer.