IP Library Granted Patent US 8,207,620
Granted Patent B2
US 8,207,620 · App. 11/880,467 · Granted Jun 26, 2012

Flip-chip semiconductor package and chip carrier for preventing corner delamination

Assignee: Siliconware Precision Industries Co., Ltd.
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Quick Facts
Patent No.
US 8,207,620
App. No.
11/880,467
Granted
Jun 26, 2012
Kind
B2
Abstract

The present invention discloses a flip-chip semiconductor package and a chip carrier thereof. The chip carrier includes a groove formed around a chip-mounting area. The groove may be formed along a periphery of the chip-mounting area or at corners thereof. The groove is filled with a filler of low Young's modulus so as to absorb and eliminate thermal stress, thereby preventing delamination between an underfill and a flip chip mounted on the chip-mounting area.

Claims (14)

1. A flip-chip semiconductor package, comprising:

a chip carrier having at least one chip-mounting area and a groove formed in position around a periphery of the chip-mounting area;

a flip chip attached to and electrically connected to the chip-mounting area of the chip carrier via a plurality of solder bumps disposed within the chip-mounting area, wherein at least a corner or a side of the flip chip corresponds in position to the groove;

a filler of low Young's modulus filling into the groove, wherein the filler corresponds in position to at least the corner or the side of the flip chip to prevent corner delamination of the flip chip; and

an underfill of high Young's modulus for interposing between the flip-chip and the chip carrier to cover the solder bumps and form on the filler.

2. The flip-chip semiconductor package of claim 1 , wherein the chip carrier is a substrate comprising a body, the chip-mounting area disposed on the body, and the groove disposed in position around the chip-mounting area.

3. The flip-chip semiconductor package of claim 2 , wherein the body comprises a core layer, a plurality of solder pads formed on the core layer, and a solder mask covering the core layer but exposing the solder pads.

4. The flip-chip semiconductor package of claim 3 , wherein the solder pads are disposed within the chip-mounting area, such that the flip chip is electrically connected to the solder pads through the solder bumps.

5. The flip-chip semiconductor package of claim 1 , wherein the groove is formed at corners of the chip-mounting area.

6. The flip-chip semiconductor package of claim 1 , wherein the filler has a glass transition temperature Tg of less than 80° C.

7. The flip-chip semiconductor package of claim 1 , wherein the Young's modulus of the filler is less than 2000 Mpa at room temperature.

8. The flip-chip semiconductor package of claim 1 , wherein the underfill has a glass transition temperature Tg of greater than 80° C.

9. The flip-chip semiconductor package of claim 1 , wherein the Young's modulus of the underfill is greater than 2000 Mpa at room temperature.

10. The flip-chip semiconductor package of claim 1 , wherein the filler of low Young's modulus is made of silicone.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 25, 2007
From: TZENG, YUAN-LIN; KAO, NAI-HAO; LAI, JENG-YUAN; WANG, YU-PO; HSIAO, CHENG-HSU
To: SILICONWARE PRECISION INDUSTRIES CO., LTD.
Reel/Frame 019901/0541 →
Priority Claims (1)
TW 95126475 A · Jul 20, 2006 · national
Continuity (1)
Related Publication 20080017983A1 · Jan 24, 2008