IP Library Granted Patent US 7,687,972
Granted Patent B2
US 7,687,972 · App. 11/881,157 · Granted Mar 30, 2010

Drive wave generation circuit

Assignees: Sanyo Electric Co., Ltd.; Sanyo Semiconductor Co., Ltd.
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Quick Facts
Patent No.
US 7,687,972
App. No.
11/881,157
Granted
Mar 30, 2010
Kind
B2
Abstract

Fundamental waveform data transferred through a serial interface is stored in a register. A fundamental waveform generation circuit uses the data to generate a fundamental waveform. A selector is capable of providing fundamental waveform data stored in a fixed memory to the register to replace the fundamental waveform data provided through the serial interface. An initial counter provides a low level signal to an exclusive OR gate until its count value reaches a first predetermined value. A direction control signal M/I is provided to the exclusive OR gate from an external source and the direction control signal M/I at high or low level inverts a direction control signal to be provided to a direction selector.

Claims (17)

1. A drive wave generation circuit which generates a drive wave for driving a piezo actuator, comprising:

a register configured to store fundamental waveform data, wherein the fundamental waveform data includes data for setting a duty ratio;

a memory configured to store preset fundamental waveform data, wherein the preset fundamental waveform data includes data for setting a duty ratio;

a serial interface configured to provide transferred fundamental waveform data to the register, wherein the transferred fundamental waveform data includes data for setting a duty ratio;

a selector configured to select whether the register stores preset fundamental waveform data provided by the memory or transferred fundamental waveform data provided by the serial interface as the fundamental waveform data in the register; and

a fundamental waveform generation circuit configured to generate a fundamental waveform;

wherein the fundamental waveform has a duty cycle in accordance with the fundamental waveform data stored in the register, and

wherein the drive wave is generated on the basis of the fundamental waveform data stored in the register.

2. The drive wave generation circuit according to claim 1 , further comprising:

a unit counter which counts cycles of a fundamental waveform and, when the count value reaches a predetermined unit count, outputs a unit detection pulse;

a drive counter which counts input drive pulses from an initial value in one direction and counts count values in the direction of the initial value in accordance with a unit detection pulse from the unit counter; and

an output gate which outputs a drive wave including a fundamental waveform after the drive counter counts in one direction up to the initial value;

wherein a drive wave including fundamental waveforms is output, the number of the fundamental waveforms being the number of input drive pulses multiplied by the number of fundamental cycles in one unit.

3. The drive wave generation circuit according to claim 2 , wherein:

the fundamental waveform generation circuit generates two types of fundamental waveforms;

the drive wave generation circuit comprises a direction selector which receives the two types of fundamental waveforms from the fundamental waveform generation circuit and perform selection, in accordance with a direction control signal, as to which of two output terminals is used to output each of the received two types of waveforms;

wherein, the output gate receives an output from the direction selector and permits output from the direction selector in a period from the time the drive counter starts counting in one direction to the time the initial value is reached to output a drive wave including a pair of fundamental waveforms.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 033813 FRAME: 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jan 21, 2015
From: SYSTEM SOLUTIONS CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 034816/0510 →
CHANGE OF NAME Recorded Dec 3, 2014
From: SANYO SEMICONDUCTOR CO., LTD
To: SYSTEM SOLUTIONS CO., LTD.
Reel/Frame 034537/0044 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2014
From: SANYO SEMICONDUCTOR CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033813/0420 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2014
From: SANYO ELECTRIC CO., LTD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 032836/0342 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2011
From: SANYO ELECTRIC CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 026594/0385 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2007
From: ISHII, TAKAAKI; UESHIMA, YASUYUKI
To: SANYO ELECTRIC CO., LTD.; SANYO SEMICONDUCTOR CO., LTD.
Reel/Frame 019842/0863 →
Priority Claims (2)
JP 2006-203236 · Jul 26, 2006 · national
JP 2006-203237 · Jul 26, 2006 · national
Continuity (1)
Related Publication 20080048523A1 · Feb 28, 2008