IP Library Granted Patent US 7,898,002
Granted Patent B2
US 7,898,002 · App. 11/890,480 · Granted Mar 1, 2011

Nitride semiconductor device and method for fabricating the same

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Quick Facts
Patent No.
US 7,898,002
App. No.
11/890,480
Granted
Mar 1, 2011
Kind
B2
Abstract

A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer formed over the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a larger band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer and including a p-type nitride semiconductor with at least a single-layer structure; a gate electrode formed on the third nitride semiconductor layer; and a source electrode and a drain electrode formed in regions located on both sides of the gate electrode, respectively. The third nitride semiconductor layer has a thickness greater in a portion below the gate electrode than in a portion below the side of the gate electrode.

Claims (39)

1. A nitride semiconductor device comprising:

a substrate;

a first nitride semiconductor layer formed over the substrate;

a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a larger band gap energy than the first nitride semiconductor layer;

a third nitride semiconductor layer which is formed on the second nitride semiconductor layer and which consists of a single layer of p-type nitride semiconductor;

a gate electrode formed on the third nitride semiconductor layer; and

a source electrode and a drain electrode formed in regions located on both sides of the gate electrode, respectively,

wherein the third nitride semiconductor layer has a thickness greater in a portion below the gate electrode than in a portion below the side of the gate electrode.

2. The device of claim 1 ,

wherein the third nitride semiconductor layer includes a first p-type layer and a second p-type layer sequentially formed in this order from the substrate side, and

the first p-type layer has a thickness greater in the portion below the gate electrode than in portions located between the source electrode and the gate electrode and between the drain electrode and the gate electrode.

3. The device of claim 2 ,

wherein the first nitride semiconductor layer is made of GaN,

the second nitride semiconductor layer is made of Al x Ga 1−x N(0<x≦1),

the first p-type layer of the third nitride semiconductor layer is made of Al y Ga 1−y N(0≦y ≦1), and

the second p-type layer of the third nitride semiconductor layer is made of Al z Ga 1−z N(0≦z≦1 and y≠z).

4. The device of claim 2 , wherein the first p-type layer of the third nitride semiconductor layer has a thickness of 15 nm or more.

5. The device of claim 1 , wherein the third nitride semiconductor layer is made of a single-layer p-type semiconductor layer.

6. The device of claim 5 ,

wherein the first nitride semiconductor layer is made of GaN,

the second nitride semiconductor layer is made of Al x Ga 1−x N(0<x≦1), and

the third nitride semiconductor layer is made of Al y Ga 1−y N(0≦y≦1).

7. The device of claim 1 , wherein a transistor element formed of the gate electrode has a first threshold voltage higher than a second threshold voltage of a virtual transistor element formed as a virtual component and extending in a region below the side of the gate electrode through a surface depletion layer.

8. The device of claim 7 , wherein the first threshold voltage is 2.5 V or more higher than the second threshold voltage.

9. The device of claim 1 , wherein the source electrode and the drain electrode are formed to come into contact with the interface between the first nitride semiconductor layer and the second nitride semiconductor layer.

10. The device of claim 1 , wherein the substrate exhibits conductivity.

11. The device of claim 10 , wherein the substrate is made of one of silicon and silicon carbide.

12. The device of claim 10 , wherein the source electrode is electrically connected to the substrate through a via hole penetrating the first nitride semiconductor layer, the second nitride semiconductor layer, and the third nitride semiconductor layer.

13. The device of claim 1 , further comprising:

an insulating film formed over the gate electrode and having a relative dielectric constant of 4 or lower; and

an upper-side electrode provided on the insulating film and electrically connected to the drain electrode.

14. A nitride semiconductor device comprising:

a substrate;

a first nitride semiconductor layer formed over the substrate;

a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a larger band gap energy than the first nitride semiconductor layer;

a third nitride semiconductor layer which is formed on the second nitride semiconductor layer and which consists of a single layer of p-type nitride semiconductor;

a gate electrode formed on the third nitride semiconductor layer; and

a source electrode and a drain electrode formed in regions located on both sides of the gate electrode, respectively,

wherein the third nitride semiconductor layer includes a first portion having a first thickness below the gate electrode, and a second portion having a second thickness thinner than the first thickness.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2025
From: INFINEON TECHNOLOGIES AUSTRIA AG
To: PANASONIC HOLDINGS CORPORATION
Reel/Frame 072853/0508 →
CHANGE OF NAME Recorded Dec 13, 2024
From: PANASONIC CORPORATION
To: PANASONIC HOLDINGS CORPORATION
Reel/Frame 069631/0392 →
CHANGE OF NAME Recorded Nov 20, 2008
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 021897/0516 →