Granted Patent B2

US 7,969,788 · App. 11/894,377 · Granted Jun 28, 2011

Assignee: Micron Technology, Inc.

Abstract

Claims (100)

1. A method of operating a memory, comprising:

determining a quick charge loss compensation for at least one block of the memory; and

adjusting a wordline voltage of the memory according to the quick charge loss compensation;

wherein determining a quick charge loss compensation comprises:

programming a tracking block in the memory associated with the at least one block of the memory in accordance with a specific pattern;

determining a first mean threshold voltage for the tracking block; and

re-programming the tracking block in accordance with the specific pattern when its associated block is programmed; and

wherein adjusting the wordline voltage level is based on the first mean threshold voltage and a second mean threshold voltage for the tracking block after the reprogramming.

2. The method of claim 1 , wherein determining the quick charge loss compensation comprises:

wear leveling program blocks in the memory;

erasing the tracking block when its associated program block is erased.

3. The method of claim 2 , wherein adjusting the wordline voltage comprises adjusting the wordline voltage level equal to a difference between the first mean threshold voltage and the second mean threshold voltage for the tracking block after the re-programming.

4. The method of claim 2 , wherein the tracking block is programmed as a single redundant memory block for one block of the memory.

5. The method of claim 2 , wherein the tracking block is a plurality of mini-arrays, each block of the memory having a separate mini-array or a portion thereof associated therewith.

6. A method of operating a memory, comprising:

determining a quick charge loss compensation for at least one block of the memory; and

adjusting a wordline voltage of the memory according to the quick charge loss compensation;

wherein determining the quick charge loss compensation comprises:

programming at least a portion of a mini-array in the memory for each of the blocks of the memory in accordance with a specific pattern;

determining a first mean threshold voltage for the at least a portion of each mini-array;

determining a difference between a second mean threshold voltage of the at least a portion of the mini-array upon reading a program block associated with the at least a portion of the mini-array and the first mean threshold voltage for the at least a portion of the mini-array; and

adjusting a wordline voltage level by the difference.

7. The method of claim 6 , wherein determining the quick charge loss compensation comprises:

completing a mini-array margin search on the at least a portion of the mini-array block when its associated main array block is read;

re-programming the at least a portion of the mini-array in accordance with the specific pattern when its associated block is programmed.

8. The method of claim 7 , wherein programming of the at least a portion of a mini-array is contemporaneous to programming of its associated program block.

9. A method of operating a memory, comprising:

wear leveling program blocks in the memory;

associating a redundant block in the memory with one of a plurality of program blocks in the memory;

programming the redundant block in accordance with a specific pattern;

determining a mean uncycled threshold voltage for the redundant block;

erasing the redundant block when its associated program block is erased;

re-programming the redundant block in accordance with the specific pattern when its associated block is programmed;

determining a current post-cycled mean threshold voltage for the redundant block; and

adjusting a wordline voltage level based on the mean uncycled threshold voltage and the current post-cycled mean threshold voltage.

10. The method of claim 9 , wherein adjusting further comprises raising the wordline voltage level by an amount equal to a difference between the uncycled mean threshold voltage and the current post-cycled mean threshold voltage for the redundant block.

11. A method of operating a memory, comprising:

associating each program block in the memory with at least a portion of a mini-array;

programming each respective at least a portion of a mini-array in accordance with a specific pattern;

determining a mean uncycled threshold voltage for each at least a portion of a mini-array;

completing a mini-array margin search on the at least a portion of a mini-array block when its associated program block is read to determine a difference between its current post-cycled threshold voltage mean and the mean uncycled threshold voltage for the at least a portion of the mini-array;

re-programming the at least a portion of the mini-array in accordance with the specific pattern when its associated block is programmed; and

adjusting a wordline voltage level by an amount equal to the difference.

12. The method of claim 11 , wherein associating with at least a portion of a mini-array comprises allocating a page or a portion of a page of a mini-array to each program block.

13. A method of operating a memory, comprising:

determining an uncycled mean threshold voltage for a tracking block of the memory programmed in accordance with a specific pattern;

storing the uncycled mean threshold voltage for the tracking block;

monitoring the erasing of one of a plurality of memory blocks in the memory;

erasing the tracking block every time the monitored one of the plurality of memory blocks is erased;

re-programming the tracking block in accordance with the specific pattern;

determining a current post-cycled mean threshold voltage level for the tracking block;

determining a correction voltage based on the stored uncycled mean threshold voltage and the current post-cycled mean threshold voltage level; and

adding the correction voltage to a program verify level for verification.

14. The method of claim 13 , wherein determining the correction voltage comprises subtracting the current post-cycled mean threshold voltage from the stored uncycled mean threshold voltage.

15. A memory device, comprising:

an array of non-volatile memory cells, having a plurality of program blocks;

a tracking block associated with one of the program blocks, the tracking block to store a mean threshold voltage to allow determination of quick charge loss compensation for the associated program block; and

logic circuitry on the memory to compare an original mean threshold voltage of the tracking block to the mean threshold voltage to determine the quick charge loss compensation.

16. A memory device, comprising:

an array of non-volatile memory cells, having a plurality of main program array blocks, arranged in rows and columns;

control circuitry to read, write and erase the memory cells;

address circuitry to latch address signals provided on address input connections;

a plurality of mini-arrays, a mini-array or a portion thereof associated with one of the main program array blocks, each mini-array or portion thereof to store current post-cycled mean threshold voltage of its associated main program array block to allow determination of charge loss compensation for its main program array block; and

logic circuitry on the memory to compare an uncycled mean threshold voltage of each mini-array or portion thereof to the current post-cycled mean threshold voltage to determine the charge loss compensation for its main program array block.

17. The memory device of claim 16 , wherein each mini-array comprises a plurality of blocks.

18. A memory device, comprising:

an array of non-volatile memory cells, having a plurality of program blocks and a tracking block;

logic circuitry to compare an original mean threshold voltage of the tracking block to a mean threshold voltage;

circuitry for control and/or access of the array of non-volatile memory cells, the control circuitry adapted to perform a method comprising:

determining a quick charge loss compensation for at least one program block based on the original mean threshold voltage and the mean threshold voltage; and

adjusting a wordline voltage of the memory for read operations by an amount equal to the quick charge loss compensation.

19. A memory device, comprising:

an array of non-volatile memory cells, having a plurality of program blocks and a tracking block, the memory cells accessed by bitlines and word lines; and

circuitry for control and/or access of the array of non-volatile memory cells, the control circuitry adapted to perform a method comprising:

wear leveling program blocks in the memory;

associating a redundant block in the memory with one of a plurality of program blocks in the memory;

programming the redundant block in accordance with a specific pattern;

determining a mean uncycled threshold voltage for the redundant block;

erasing the redundant block when its associated program block is erased;

re-programming the redundant block in accordance with the specific pattern when its associated block is programmed;

determining a difference between the mean uncycled threshold voltage and a current mean threshold voltage for the redundant block; and

adjusting a wordline voltage level by the difference.

20. A memory device, comprising:

an array of non-volatile memory cells, having a plurality of program blocks and a tracking block, the memory cells accessed by bitlines and word lines; and

circuitry for control and/or access of the array of non-volatile memory cells, the control circuitry adapted to perform a method comprising:

associating each program block in the memory with a mini-array or a portion thereof;

programming each respective mini-array or portion thereof with a specific pattern;

determining a mean uncycled threshold voltage for each mini-array or portion thereof;

completing a mini-array margin search on a mini-array block or portion thereof when its associated main array block is read to determine a difference between a current mean threshold voltage of the mini-array block or portion thereof and the uncycled mean for the mini-array or portion thereof;

re-programming the mini-array with the specific pattern when its associated block is programmed; and

adjusting a wordline voltage by an amount equal to the difference.

21. A system, comprising:

a processor; and

one or more memory device coupled to the processor, wherein at least one of the memory devices comprises:

an array of non-volatile memory cells;

a tracking block; and

logic circuitry to compare an original mean threshold voltage of the tracking block to a mean threshold voltage;

circuitry for control and/or access of the array of non-volatile memory cells, the control circuitry adapted to perform a method comprising:

determining a quick charge loss compensation for at least one block of the memory based on the original mean threshold voltage and the mean threshold voltage; and

adjusting a wordline voltage of the memory according to the quick charge loss compensation.

Assignments (8)

Continuity (1)