Semiconductor device having fin field effect transistor and manufacturing method thereof
View Patent ↗A semiconductor device including fin-FETs capable of suppressing both OFF-current resulting from the short channel effect and junction leakage, and a manufacturing method thereof are provided. A semiconductor device comprises: an active region defined to have a crank shape by an STI region formed on a semiconductor substrate, the active region having an upper surface higher than an upper surface of the STI region; a source region and a drain region formed on both ends of the active region, respectively; a channel region formed between the source region and the drain region in the active region; and a gate electrode covering an upper surface and side surfaces of a central portion of the active region including the channel region.
1. A semiconductor device comprising:
an active region defined to have a crank shape by an STI region formed on a semiconductor substrate, the active region having an upper surface higher than an upper surface of the STI region, and the active region comprising a central portion and a pair of side portions which are offset and extend from opposing sides of the central portion;
a source region and a drain region formed on the pair of side portions of the active region, respectively;
a channel region formed between the source region and the drain region in the active region; and
a gate electrode covering an upper surface and a surface of the opposing sides of the central portion of the active region including the channel region.
2. The semiconductor device as claimed in claim 1 , wherein the source region and the drain region are arranged symmetrically with respect to a central point of the active region.
3. A semiconductor device comprising:
a fin-shaped active region formed by a part of a semiconductor substrate, the active region comprising a central portion and a pair of side portions which are offset and extend from opposing sides of the central portion; and
a gate electrode extending in an X direction to cross the active region, and covering an upper surface and a surface of the opposing sides of the central portion of the active region,
wherein the active region has a channel region covered by the gate electrode and a source region and a drain region formed on both ends of the active region, respectively,
wherein the source region and the drain region are offset from each other in the X direction.
4. The semiconductor device as claimed in claim 3 , wherein a part of the source region and a part of the drain region are covered with the gate electrode.
5. A semiconductor device comprising:
a fin-shaped active region comprising a first portion and second and third portions which are offset and extend from opposing sides of the first portion;
a gate electrode covering a surface of the opposing sides of the first portion of the active region; and
a source region and a drain region provided on the second portion and the third portion opposed to each other across the first portion of the active region, respectively,
wherein the first portion includes at least one bent portion.
6. The semiconductor device as claimed in claim 5 , wherein the at least one bent portion includes a first bent portion and a second bent portion, and a region between the first bent portion and the second bent portion in the active region extends in a direction substantially identical to an extension direction of the gate electrode.
7. A semiconductor device comprising:
a fin-shaped active region including:
a first portion extending in a first direction;
a second portion connected to a first side of the first portion at an end of the first portion and extending in a second direction; and
a third portion connected to a second side of the first portion which is opposite the first side at an other end of the first portion and being offset with the second portion and extending in the second direction;
a gate electrode extending in the first direction and covering the first and second sides of the first portion, a part of the second portion, and a part of the third portion;
a source region provided on another part of the second portion; and
a drain region provided on another part of the third portion.
8. The semiconductor device as claimed in claim 1 , wherein the gate electrode extends in a first direction and the pair of side portions extend from the opposing sides of the central portion in a second direction substantially perpendicular to the first direction, and
wherein a part of the source region and a part of the drain region are covered with the gate electrode, the parts of the source and drain regions being offset in the first direction.
9. The semiconductor device as claimed in claim 1 , wherein an effective channel length of the device comprises a sum of a width of the gate electrode and an offset width between the pair of side portions in the first direction.
10. The semiconductor device as claimed in claim 1 , wherein the central portion comprises a bent portion, and the gate electrode is formed on the bent portion.
11. The semiconductor device as claimed in claim 1 , further comprising:
a gate insulating film formed on the opposing sides of the central portion between the gate electrode, and the central portion.
12. The semiconductor device as claimed in claim 1 , further comprising:
a silicon epitaxial layer formed on an upper surface of the source region and the drain region and having a width which is greater than a width of the pair of side portions such that the silicon epitaxial layer extends over an edge of the pair of side portions; and
a contact plug formed on the silicon epitaxial layer.