IP Library Granted Patent US 7,696,569
Granted Patent B2
US 7,696,569 · App. 11/902,167 · Granted Apr 13, 2010

Semiconductor device including a trench with a curved surface portion and method of manufacturing the same

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,696,569
App. No.
11/902,167
Granted
Apr 13, 2010
Kind
B2
Abstract

A semiconductor device includes a trench provided in a semiconductor substrate, a gate electrode formed in the trench through a gate dielectric film, and a diffusion layer formed in the vicinity of the trench. The trench includes an opening portion provided in a surface of the semiconductor substrate, a recess curved surface portion including a cross-sectional contour having a substantially circular arc shape, and a connection curved surface portion connecting the recess curved surface portion and the opening portion. The connection curved surface portion includes a continuous curved surface between the opening portion and the recess curved surface portion.

Claims (39)

1. A semiconductor device comprising:

a trench provided in a semiconductor substrate;

a gate electrode formed in the trench through a gate dielectric film; and

a diffusion layer formed in a vicinity of the trench,

wherein the trench comprises:

an opening portion provided in a surface of the semiconductor substrate;

a recess curved surface portion comprising a cross-sectional contour having a substantially circular arc shape; and

a connection curved surface portion connecting the recess curved surface portion and the opening portion, and

wherein the connection curved surface portion comprises a continuous curved surface between the opening portion and the recess curved surface portion.

2. The semiconductor device as recited in claim 1 , further comprising:

a trench gate transistor including the trench, the gate electrode and the diffusion layer,

wherein the semiconductor device comprises a dynamic random access memory using the trench gate transistor as a transfer gate transistor of a memory cell.

3. The semiconductor device as recited in claim 1 , wherein a width of the connection curved surface portion gradually increases between the opening portion and the recess curved surface portion.

4. The semiconductor device as recited in claim 1 , wherein a least width of the opening portion comprises a least width of the trench.

5. The semiconductor device as recited in claim 1 , wherein a bottom of the diffusion layer is formed in a vicinity of the recess curved surface portion of the trench.

6. The semiconductor device as recited in claim 1 , wherein the opening portion adjoins the connection curved surface portion at a location in the trench where a width of the trench includes a least width of the trench.

7. The semiconductor device as recited in claim 1 , wherein a width of an opening of the connection curved surface portion comprises a minimum width of the trench.

8. The semiconductor device as recited in claim 7 , wherein a distance between the opening of the connection curved surface portion and a center of the circular arc shape is greater than a radius of the circular are shape.

9. The semiconductor device as recited in claim 1 , wherein the recess curved surface portion comprises a first portion which forms a bottom of the trench and comprises the substantially circular arc shape.

10. The semiconductor device as recited in claim 9 , wherein the recess curved surface portion comprises a second portion comprising an arc shape having a radius which is greater than a radius of the circular arc shape of the first portion.

11. A semiconductor device, comprising:

a trench provided in a semiconductor substrate;

a gate electrode formed in the trench through a sate dielectric film; and

a diffusion layer formed in a vicinity of the trench,

wherein a cross-sectional contour of the trench is substantially U-shaped, a width of an opening portion of the trench is smaller than the width of a bottom portion of the trench, and a surface extending from the opening portion to the bottom portion comprises a continuous curved surface, and

wherein the surface extending from the opening portion to the bottom portion comprises a non-angular portion.

12. The semiconductor device as recited in claim 11 , further comprising:

a trench gate transistor including the trench, the gate electrode and the diffusion layer,

wherein the semiconductor device comprises a dynamic random access memory using the trench gate transistor as a transfer gate transistor of a memory cell.

13. A trench structure for a trench gate transistor of a semiconductor device, the trench structure comprising:

an opening portion provided in a surface of a semiconductor substrate;

a recess curved surface portion comprising:

a first portion which forms a bottom of the trench structure and comprises the substantially circular arc shape; and

a second portion comprising an arc shape having a radius which is greater than a radius of the circular arc shape of the first portion; and

a connection curved surface portion connecting the second portion of the recess curved surface portion and the opening portion.

14. The trench structure according to claim 13 , wherein the trench structure is formed in a semiconductor substrate of a trench gate transistor in a semiconductor device, the transistor further comprising:

a gate electrode formed in the trench structure; and

a diffusion layer formed in a vicinity of the trench structure, a bottom of the diffusion layer being farmed in a vicinity of the recess curved surface portion of the trench structure.

15. The trench structure according to claim 14 , wherein the bottom of the diffusion layer is formed in a vicinity of the second portion of the recess curved surface portion of the trench structure.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2014
From: ELPIDA MEMORY, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032645/0422 →