IP Library Granted Patent US 8,225,499
Granted Patent B2
US 8,225,499 · App. 11/917,724 · Granted Jul 24, 2012

Method for manufacturing a circuit board structure, and a circuit board structure

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Quick Facts
Patent No.
US 8,225,499
App. No.
11/917,724
Granted
Jul 24, 2012
Kind
B2
Abstract

This publication discloses a method for manufacturing a circuit-board structure. 1 . The structure comprises a conductor pattern ( 3 ) and at least one component ( 6 ), which is surrounded by an insulating-material layer ( 10 ), attached to it by means of a contact bump ( 5 ). According to the invention, the contact bumps ( 5 ) are made on the surface of the conductor pattern ( 3 ), before the component ( 6 ) is attached to the conductor pattern ( 3 ) by means of the contact bump ( 5 ). After attaching, the component ( 6 ) is surrounded with an insulating-material layer ( 10 ).

Claims (36)

1. Method for manufacturing a circuit-board structure, which structure comprises a component inside an insulating-material layer, the method comprising:

making a first conductor pattern;

making a second conductor pattern corresponding to the first conductor pattern and intended for conducting thermal energy away from the vicinity of the component;

making at least one contact bump on a surface of the first conductor pattern using a first manufacturing process;

making at least one thermal bump on a surface of the second conductor pattern using the first manufacturing process;

after making the at least one contact bump, attaching the component to the first conductor pattern by means of the at least one contact bump; and

after attaching the component, making the insulating-material layer around the component.

2. Method according to claim 1 , characterized in that the component comprises several contacts, for each of which an individual contact bump is made on the surface of the first conductor pattern.

3. Method according to claim 1 , characterized in that the component is a semiconductor chip, on a surface of which are contact areas, which are connected to contact bumps corresponding to the contact areas.

4. Method according to claim 3 , characterized in that the component to be connected to the contact bumps is an unpackaged and bumpless semiconductor chip.

5. Method according to claim 1 , characterized in that a joint between the component and the contact bump is made using an ultrasonic bonding method.

6. Method according to claim 1 , characterized in that the insulating-material layer is made by pressing together at least two insulating-material sheets, at least one of which comprises openings for the component.

7. Method according to claim 6 , characterized in that the component is one of at least two components which are attached to the first conductor pattern, one of the at least two components being thicker than another of the at least two components which is thinner than the thicker component, and at least one of the insulating-material sheets to be pressed comprises at opening at the location of the thicker component, but has at least substantially no opening at the location of the thinner component.

8. Method according to claim 1 , characterized in that the first conductor pattern is manufactured on a surface of a support layer, which support layer is removed after the insulating-material layer has been made around the component.

9. Method according to claim 8 , characterized in that a mask layer, which contains openings defining the first conductor pattern, is formed on the surface of the support layer for the manufacture of the first conductor pattern, and the first conductor pattern is manufactured in these openings by electrolytic growing.

10. Method according to claim 8 , characterized in that an intermediate layer is used between the first conductor pattern and the support layer, and the support layer is removed by etching as far as the intermediate layer, which acts as an etching stop.

11. Method according to claim 1 , characterized in that a patterned mask layer, which contains openings for the contact bumps, and in which the contact bumps are made, is formed on the surface of the first conductor pattern for the manufacture of the contact bumps.

12. Method according to claim 11 , characterized in that the contact bumps are made by electrolytic growing and the electrical current required for the electrolytic growing is led to the contact bump being grown, through the first conductor pattern and a support layer.

13. Method according to claim 1 , characterized in that the contact bumps and the first conductor pattern are at least principally of copper.

14. Method according to claim 1 , characterized in that on the surface of the contact bump intended to face the component there is a layer, which contains gold.

15. Method according to claim 1 , characterized in that the contact bumps are connected to connector surfaces of the component, which are made from aluminium, copper, or gold.

16. Method according to claim 1 , characterized in that several conductor-pattern layers are made in the circuit-board structure.

17. Method according to claim 1 , characterized in that a thermal via is manufactured using a via technique.

18. Method according to claim 17 , characterized in that the thermal via is manufactured to be in contact with the second conductor pattern corresponding to the first conductor pattern.

19. Method according to claim 1 , characterized in that a vertical thermal conductor is manufactured to be in contact with a lateral thermal conductor which is in contact with a thermal via or a thermal bump, so that thermal effect can be conducted through the vertical and/or the lateral thermal conductor from innermost layers of the circuit-board structure towards its outer surface.

20. Method according to claim 19 , characterized in that the vertical thermal conductor is connected to a heat sink, which is located outside the circuit-board structure or on the outer surface of the circuit-board structure.

21. Circuit-board structure comprising:

a first conductor pattern and at least one component;

a second conductor pattern corresponding to the first conductor pattern and intended for conducting thermal energy away from a vicinity of the at least one component;

at least one contact bump on a surface of the first conductor pattern, the at least one contact bump having a material and a height determined by a first manufacturing process;

at least one thermal bump on a surface of the second conductor pattern, the at least one thermal bump made of the material and having the height determined by the first manufacturing process; and

an insulating-material layer disposed around the component such that the at least one component is inside the insulating-material layer,

wherein the at least one component is attached to the first conductor pattern by the at least one contact bump,

wherein both the first conductor pattern and the contact bumps are manufactured by growing the first conductor pattern and the contact bumps electrolytically to a desired shape, and

wherein the at least one component comprises a surface having at least one contact bump, whereby the contact bump of the first conductor pattern contacts the contact bump of the at least one component.

22. Method according to claim 1 wherein the component comprises a surface having at least one contact bump, further including the step of bringing the contact bump of the first conductor pattern into contact with the contact bump of the component.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 052853 FRAME: 0153. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 29, 2021
From: R2 SOLUTIONS LLC
To: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
Reel/Frame 056832/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 053654 FRAME 0254. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST GRANTED PURSUANT TO THE PATENT SECURITY AGREEMENT PREVIOUSLY RECORDED. Recorded Dec 30, 2020
From: STARBOARD VALUE INTERMEDIATE FUND LP
To: R2 SOLUTIONS LLC
Reel/Frame 054981/0377 →
STATEMENT REGARDING SECURITY INTEREST INCORRECTLY RECORDED AGAINST PATENTS Recorded Oct 20, 2020
From: ACACIA RESEARCH GROUP LLC; R2 SOLUTIONS LLC
To: IMBERATEK, LLC
Reel/Frame 054134/0172 →
RELEASE OF SECURITY INTEREST IN PATENTS Recorded Jul 8, 2020
From: STARBOARD VALUE INTERMEDIATE FUND LP
To: ACACIA RESEARCH GROUP LLC; AMERICAN VEHICULAR SCIENCES LLC; BONUTTI SKELETAL INNOVATIONS LLC; CELLULAR COMMUNICATIONS EQUIPMENT LLC; INNOVATIVE DISPLAY TECHNOLOGIES LLC; LIFEPORT SCIENCES LLC; LIMESTONE MEMORY SYSTEMS LLC; MOBILE ENHANCEMENT SOLUTIONS LLC; MONARCH NETWORKING SOLUTIONS LLC; NEXUS DISPLAY TECHNOLOGIES LLC; PARTHENON UNIFIED MEMORY ARCHITECTURE LLC; R2 SOLUTIONS LLC; SAINT LAWRENCE COMMUNICATIONS LLC; STINGRAY IP SOLUTIONS LLC; SUPER INTERCONNECT TECHNOLOGIES LLC; TELECONFERENCE SYSTEMS LLC; UNIFICATION TECHNOLOGIES LLC
Reel/Frame 053654/0254 →
PATENT SECURITY AGREEMENT Recorded Jun 5, 2020
From: ACACIA RESEARCH GROUP LLC; AMERICAN VEHICULAR SCIENCES LLC; BONUTTI SKELETAL INNOVATIONS LLC; CELLULAR COMMUNICATIONS EQUIPMENT LLC; INNOVATIVE DISPLAY TECHNOLOGIES LLC; LIFEPORT SCIENCES LLC; LIMESTONE MEMORY SYSTEMS LLC; MERTON ACQUISITION HOLDCO LLC; MOBILE ENHANCEMENT SOLUTIONS LLC; MONARCH NETWORKING SOLUTIONS LLC; NEXUS DISPLAY TECHNOLOGIES LLC; PARTHENON UNIFIED MEMORY ARCHITECTURE LLC; R2 SOLUTIONS LLC; SAINT LAWRENCE COMMUNICATIONS LLC; STINGRAY IP SOLUTIONS LLC; SUPER INTERCONNECT TECHNOLOGIES LLC; TELECONFERENCE SYSTEMS LLC; UNIFICATION TECHNOLOGIES LLC
To: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
Reel/Frame 052853/0153 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2020
From: GE EMBEDDED ELECTRONICS OY
To: IMBERATEK, LLC
Reel/Frame 051730/0868 →
CHANGE OF NAME Recorded Jan 23, 2020
From: IMBERA ELECTRONICS OY
To: GE EMBEDDED ELECTRONICS OY
Reel/Frame 051669/0086 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 24, 2008
From: TUOMINEN, RISTO; IIHOLA, ANTTI; PALM, PETTERI
To: IMBERA ELECTRONICS OY
Reel/Frame 021287/0032 →