IP Library Granted Patent US 7,691,743
Granted Patent B2
US 7,691,743 · App. 11/923,062 · Granted Apr 6, 2010

Semiconductor device having a capacitance element and method of manufacturing the same

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Quick Facts
Patent No.
US 7,691,743
App. No.
11/923,062
Granted
Apr 6, 2010
Kind
B2
Abstract

A dielectric film is formed by depositing an amorphous strontium oxide film to a thickness of one to several atomic layers on a first electrode layer, then depositing an amorphous titanium oxide film to a thickness of one to several atomic layers on the amorphous strontium oxide film, and then heat-treating a laminated film of the amorphous strontium oxide film and the amorphous titanium oxide film at a temperature close to a crystallization start temperature, thereby converting the laminated film to a single-layer amorphous strontium titanate film containing a plurality of crystal grains therein. The laminated film may have a plurality of amorphous strontium oxide films and a plurality of amorphous titanium oxide films that are alternately laminated. A semiconductor device includes a capacitor having as its dielectric film a single-layer amorphous strontium titanate film containing a plurality of crystal grains therein.

Claims (19)

1. A method of manufacturing a semiconductor device having a capacitance element including a dielectric film disposed between a first electrode layer and a second electrode layer, wherein formation of said capacitance element comprises the steps of:

forming a laminated film comprising at least one pair of amorphous films on said first electrode layer, said amorphous films being a first two-element amorphous metal oxide film and a second two-element amorphous metal oxide film formed in the order named or in the reverse order; wherein said first two-element amorphous metal oxide film and said second two-element amorphous metal oxide film are each deposited to a thickness of one to ten atomic layers, and

heat-treating said laminated film at a temperature close to a crystallization start temperature, thereby converting said laminated film to a single-layer three-element amorphous metal oxide film covering a plurality of crystal grains therein.

2. The method according to claim 1 , wherein said first two-element amorphous metal oxide film is a strontium oxide film and said second two-element amorphous metal oxide film is a titanium oxide film.

3. The method according to claim 2 , wherein said three-element amorphous metal oxide film is a strontium titanate film.

4. The method according to claim 3 , wherein a molar ratio of strontium to titanium in said strontium titanate film is 0.8 to 1.2.

5. The method according to claim 4 , wherein said strontium titanate film is formed by heat-treating said strontium oxide film and said titanium oxide film at a temperature of 500° C. to 600° C.

6. The method according to claim 3 , wherein a molar ratio of strontium to titanium in said strontium titanate film is 0.8 to 1.0.

7. The method according to claim 6 , wherein said strontium titanate film is formed by heat-treating said strontium oxide film and said titanium oxide film at a temperature of 550° C. to 600° C.

8. The method according to claim 1 , further comprising a step of forming an aluminum oxide film between said first two-element amorphous metal oxide film and said first electrode layer or between said second electrode layer and said second two-element amorphous metal oxide film.

9. A method of manufacturing a semiconductor device having a capacitance element including a dielectric film disposed between a first electrode layer and a second electrode layer, wherein formation of said capacitance element comprises the steps of:

forming a laminated film comprising at least one pair of amorphous films on said first electrode layer, said amorphous films being an amorphous strontium oxide film having a thickness of one to ten atomic layers and an amorphous titanium oxide film having a thickness of one to ten atomic layers, which are formed in the order named or in the reverse order, and

heat-treating said laminated film at a temperature close to a crystallization start temperature, thereby converting said laminated film to a single-layer amorphous strontium titanate film containing a plurality of crystal grains therein.

10. The method according to claim 9 , wherein said laminated film comprises a plurality of pairs each including said amorphous strontium oxide film and said amorphous titanium oxide film and wherein said amorphous strontium oxide films and said amorphous titanium oxide films are alternately laminated.

11. The method according to claim 10 , wherein a molar ratio of strontium to titanium in said amorphous strontium titanate film is 0.8 to 1.2.

12. The method according to claim 11 , wherein said amorphous strontium titanate film is formed by heat-treating said amorphous strontium oxide films and said amorphous titanium oxide films at a temperature of 500° C. to 600° C.

13. The method according to claim 10 , wherein a molar ratio of strontium to titanium in said amorphous strontium titanate film is 0.8 to 1.0.

14. The method according to claim 13 , wherein said amorphous strontium titanate film is formed by heat-treating said amorphous strontium oxide films and said amorphous titanium oxide films at a temperature of 550° C. to 600° C.

15. The method according to claim 9 , further comprising a step of forming an aluminum oxide dielectric film between said first electrode layer and said amorphous strontium oxide film or between said second electrode layer and said amorphous titanium oxide film before forming said amorphous strontium oxide film or after forming said amorphous titanium oxide film.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2014
From: ELPIDA MEMORY, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032645/0422 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 24, 2007
From: NAKANISHI, NARUHIKO
To: ELPIDA MEMORY, INC.
Reel/Frame 020007/0508 →