Spin memory with write pulse

1. An electron spin-based memory cell comprising:

a first ferromagnetic layer which has a changeable magnetization state;

a second ferromagnetic layer with a fixed magnetization state;

wherein the electron spin-based memory cell has a non-volatile logic state that is dependent on a relationship between said first ferromagnetic layer and said second ferromagnetic layer, including whether said changeable magnetization state and said fixed magnetization state are parallel or antiparallel;

further wherein the electron spin-based memory cell is adapted to carry at least a portion of a write pulse associated with a switching field that is applied to the cell for changing said non-volatile logic state.

2. The electron spin-based memory cell of claim 1 , wherein said cell is situated on a silicon substrate and is in a stacked arrangement over a second electron spin-based memory cell.

3. The electron spin-based memory cell of claim 1 , further including a low transmission barrier situated between said first ferromagnetic layer and said second ferromagnetic layer.

4. The electron spin-based memory cell of claim 1 , wherein said write pulse can have a single polarity.

5. The electron spin-based memory cell of claim 1 , wherein said write pulses can have at least two polarities.

6. The electron spin-based memory cell of claim 1 , wherein said cell is situated above an isolation element including a semiconductor based transistor and is separated by an insulation layer therefrom.

7. The electron spin-based memory cell of claim 1 wherein said cell is part of an electron spin-based memory array.

8. The electron spin-based memory cell of claim 1 wherein said electron spin-based memory cell is coupled in parallel by a read line to a second electron spin-based memory cell.

9. The electron spin-based memory cell of claim 6 , wherein said isolation element is coupled to a bit line, and further including a second semiconductor based transistor isolation element coupling said electron spin-based memory cell to a bit reference line.

10. The electron spin-based memory cell of claim 1 , further including a read line coupled to read data from said cell, and at least one separate write line coupled to write data to said cell.

11. An electron spin-based memory cell situated on silicon substrate comprising:

a first ferromagnetic layer which has a changeable magnetization state;

a second ferromagnetic layer with a fixed magnetization state;

wherein the electron spin-based cell has a non-volatile logic state which is dependent on a relationship between said first ferromagnetic layer and said second ferromagnetic layer, including whether said changeable magnetization state and said fixed magnetization state are parallel or antiparallel;

further wherein the electron spin-based is adapted to carry at least a portion of a write pulse associated with a switching field applied to the cell;

a semiconductor isolation element coupled to the electron spin-based memory cell adapted to isolate data stored in the cell, which isolation element includes a transistor situated in the silicon substrate.

12. The electron spin-based memory cell of claim 11 wherein said cell is part of an electron spin-based memory array.

13. The electron spin-based memory cell of claim 11 , wherein said cell is situated in a stacked arrangement over a second electron spin-based memory cell.

14. The electron spin-based memory cell of claim 11 , wherein said write pulse can have a single polarity.

15. The electron spin-based memory cell of claim 11 , wherein said write pulse can have at least two polarities.

16. A magnetoelectronic memory cell comprising:

an electron spin-based memory element situated on a silicon based substrate;

said electron spin-based memory element including:

i) a first ferromagnetic layer with a changeable magnetization state;

ii) a second ferromagnetic layer with a non-changeable magnetization state;

iii) a low transmission barrier interface coupled to at least said first ferromagnetic layer;

further wherein the electron spin-based memory element is adapted to carry at least a portion of a write pulse associated with a switching field applied to the cell.

17. The magnetoelectronic memory cell of claim 16 , further including a second low transmission barrier interface associated with said second ferromagnetic layer.

18. The magnetoelectronic memory cell of claim 16 wherein said second ferromagnetic layer is a bilayer including both a first ferromagnetic conductor layer and a second nonmagnetic conductor layer, which second nonmagnetic conductor layer is used to control a magnetic behavior of said first ferromagnetic conductor layer.

19. The memory cell of claim 16 , further including a read line coupled to read data from said electron spin-based memory element, and a separate write line coupled to write data to said electron spin-based memory element.

20. The electron spin-based memory cell of claim 16 wherein said cell is part of an electron spin-based memory array.

21. The electron spin-based memory cell of claim 16 , wherein said cell is situated in a stacked arrangement over a second electron spin-based memory cell.

22. The electron spin-based memory cell of claim 16 , wherein said write pulse can have a single polarity.

23. The electron spin-based memory cell of claim 16 , wherein said write pulse can have at least two polarities.