Integrated circuit device and signaling method with topographic dependent equalization coefficient
An integrated circuit device includes a transmitter circuit having an output driver to output data, and a register to store a value representative of an equalization co-efficient setting of the output driver. The value may be determined based on information stored in a supplemental memory device. The value is representative of an equalization co-efficient setting that compensates for signals present on an external signal line. The signals present on the external signal line comprise one selected from residual signals and cross coupled signals.
1. An integrated circuit device comprising:
a transmitter circuit including an output driver to output data;
a register to store a value representative of an equalization co-efficient setting of the output driver;
wherein the value is determined based on information stored in a memory device, and wherein the value is representative of an equalization co-efficient setting that compensates for signals present on an external signal line; and
wherein the signals present on the external signal line comprise one selected from residual signals and cross coupled signals.
2. The integrated circuit device of claim 1 , wherein the value is determined based on information stored in a memory device external to the integrated circuit device.
3. The integrated circuit device of claim 2 , wherein the memory device is a supplemental memory device.
4. The integrated circuit device of claim 3 , wherein the value is determined by accessing the supplemental memory device.
5. The integrated circuit device of claim 4 , wherein the supplemental memory device is a serial presence detect memory device.
6. The integrated circuit device of claim 5 , wherein the output driver outputs the data to a memory device disposed on a memory module, wherein the serial presence detect memory device is associated with the memory module.
7. The integrated circuit device of claim 3 , further including a data history generator circuit coupled to the transmitter circuit, to adjust the transmitter circuit based on previous data output by the output driver.
8. The integrated circuit device of claim 7 , wherein the data history generator includes a shift register to store the data that was previously output by the output driver, wherein a voltage swing setting of the output driver is modified based on the data that was previously output by the output driver.
9. The integrated circuit device of claim 3 , wherein the integrated circuit device includes a locked loop circuit to generate an internal clock signal, wherein:
the output driver outputs a first data value of the data at a rising edge transition of the internal clock signal; and
the output driver outputs a second data value of the data at a falling edge transition of the internal clock signal.
10. The integrated circuit device of claim 3 , further comprising:
a locked loop circuit to generate an internal transmit signal, wherein the transmitter circuit outputs the data in response to the internal transmit signal;
a register to store a value representative of a transmit timing offset to apply to the internal transmit signal; and
a register to store a value representative of a slew rate adjustment that is applied to the transmitter circuit.
11. A memory module, comprising:
a plurality of integrated circuit memory devices disposed on the memory module, the plurality of integrated circuit memory devices including a first memory device, the first memory device comprising:
a transmitter circuit including an output driver to output data; and
a register to store a value representative of an equalization co-efficient setting of the output driver;
wherein the value is determined based on information stored in a memory device external to the first memory device, and wherein the value is representative of an equalization co-efficient setting that compensates for signals present on an external signal line; and
wherein the signals present on the external signal line comprise one selected from residual signals and cross coupled signals.
12. The memory module of claim 11 , wherein the first memory device includes a locked loop circuit to generate a transmit clock signal, wherein the data is output onto an external signal line using the transmit clock signal.
13. The memory module of claim 11 , wherein the plurality of integrated circuit memory devices includes dynamic random access memory devices and a serial presence detect memory device.
14. An integrated circuit device, comprising:
a transmitter circuit including an output driver to output data;
a first register to store a first value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs the data in accordance with the drive strength setting; and
a second register to store a second value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs the data in accordance with the equalization setting; and
wherein the first and second values are determined based on information stored in a memory device.
15. The integrated circuit device of claim 14 wherein the integrated circuit device includes a locked loop circuit to generate a transmit clock signal, wherein the data is output using the transmit clock signal.
16. The integrated circuit device of claim 15 further including a register to store a value representative of a transmit time adjustment that is applied to the transmit clock signal.
17. The integrated circuit device of claim 16 , wherein the drive strength setting of the output driver indicates a voltage swing of the data that is output.
18. A method of operation in a system, including a first integrated circuit device coupled to a second integrated circuit device, comprising:
initializing a system that includes the first and second integrated circuit devices;
deriving a value, representative of an equalization setting of an output driver disposed on the first integrated circuit device, based on information pertaining to the second integrated circuit device;
programming the value into a register disposed on the first integrated circuit device wherein the value is representative of an equalization co-efficient setting that compensates for signals present on an external signal line;
outputting data using the output driver; and
wherein the signals present on the external signal line comprise one selected from residual signals and cross coupled signals.
19. The method of claim 18 , wherein the value is determined based on information stored in a memory device external to the integrated circuit device.
20. The method of claim 19 , further including accessing the information from a supplemental memory device.
21. The method of claim 20 , wherein the supplemental memory device is a serial presence detect memory device.
22. The method of claim 21 , wherein the serial presence detect memory device is associated with a memory module and wherein the first integrated circuit device controls the operation of the second integrated circuit device.
23. The method of claim 22 , wherein the second integrated circuit device is a memory device disposed on the memory module.
24. The method of claim 18 , wherein the second integrated circuit device is included in a plurality of memory devices disposed on a memory module and the information pertaining to the second integrated circuit device is based on configuration information of the plurality of memory devices.
25. The method of claim 18 , wherein deriving the value includes performing a look-up based on the information using a table.