IP Library Assignment 035424/0548
Patent Assignment
Reel/Frame 035424/0548

Assignment of Assignor's Interest

Recorded: 2015-04-16 Pages: 5
Assignors
HOROWITZ, MARK A.
Executed: 1999-11-19
BARTH, RICHARD M.
Executed: 1999-12-03
HAMPEL, CRAIG E.
Executed: 1999-11-30
MONCAYO, ALFREDO
Executed: 1999-11-30
DONNELLY, KEVIN S.
Executed: 1999-11-19
ZERBE, JARED L.
Executed: 1999-12-02
Assignee
RAMBUS INC.
1050 ENTERPRISE WAY, SUITE 700, SUNNYVALE, CALIFORNIA, 94089
Covered Properties (21)
Apparatus and Method for Topography Dependent Signaling
Patent: 6,516,365 →
Application: 09/910,217 →
Publication: US 2002/0056016
Apparatus and Method for Topography Dependent Signaling
Patent: 6,684,263 →
Application: 10/359,061 →
Publication: US 2003/0120848
Integrated Circuit with Transmit Phase Adjustment
Patent: 7,032,057 →
Application: 10/742,247 →
Publication: US 2004/0139257
Apparatus and Method for Topography Dependent Signaling
Patent: 7,024,502 →
Application: 10/763,849 →
Publication: US 2004/0199690
Memory Device Having Programmable Drive Strength Setting
Patent: 7,051,129 →
Application: 10/881,433 →
Publication: US 2004/0243753
Integrated Circuit Device That Stores a Value Representative of a Drive Strength Setting
Patent: 7,051,130 →
Application: 10/882,879 →
Apparatus and Method for Topography Dependent Signaling
Patent: 7,032,058 →
Application: 11/073,403 →
Publication: US 2005/0149659
Integrated Circuit Device That Stores a Value Representative of an Equalization Co-Efficient Setting
Patent: 7,174,400 →
Application: 11/181,411 →
Publication: US 2005/0251602
Integrated Circuit Device that Stores a Value Representative of an Equalization Co-Efficient Setting
Application: 11/672,018 →
Publication: US 2007/0239914
Integrated Circuit Memory Device and Signaling Method for Adjusting Drive Strength Based on Topography of Integrated Circuit Devices
Patent: 7,565,468 →
Application: 11/929,974 →
Publication: US 2008/0052440
Integrated Circuit Device and Signaling Method with Topographic Dependent Equalization Coefficient
Patent: 7,546,390 →
Application: 11/929,980 →
Publication: US 2008/0052434
Integrated Circuit Device and Signaling Method with Phase Control Based on Information in External Memory Device
Patent: 7,539,802 →
Application: 11/929,985 →
Publication: US 2008/0071951
System and Dynamic Random Access Memory Device Having a Receiver
Patent: 8,001,305 →
Application: 12/479,679 →
Publication: US 2009/0248971
Memory Controller and Method Utilizing Equalization Co-Efficient Setting
Patent: 8,214,570 →
Application: 13/196,840 →
Publication: US 2011/0289245
Chip Having Register to Store Value that Represents Adjustment to Reference Voltage
Patent: 8,458,385 →
Application: 13/535,228 →
Publication: US 2012/0268199
Chip Having Register to Store Value That Represents Adjustment to Reference Voltage
Patent: 8,775,705 →
Application: 13/853,978 →
Publication: US 2013/0227214
Chip Having Register to Store Value that Represents Adjustment to Reference Voltage
Patent: 9,110,828 →
Application: 14/321,718 →
Publication: US 2015/0006771
Chip Having Port to Receive Value That Represents Adjustment to Transmission Parameter
Patent: 9,323,711 →
Application: 14/682,926 →
Publication: US 2015/0212954
Chip Having Port to Receive Value That Represents Adjustment to Output Driver Parameter
Patent: 9,135,186 →
Application: 14/683,290 →
Publication: US 2015/0212968
Chip Having Register to Store Value That Represents Adjustment to Output Drive Strength
Patent: 9,135,967 →
Application: 14/683,324 →
Publication: US 2015/0213852
Chip Storing a Value That Represents Adjustment to Output Drive Strength
Patent: 9,152,581 →
Application: 14/686,522 →
Publication: US 2015/0220270