Chip storing a value that represents adjustment to output drive strength
An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting.
1. A system comprising:
a memory controller device to generate an access request; and
a flash memory device coupled to the memory controller device, the flash memory device, comprising:
a plurality of registers to control a corresponding set of parameters that are programmed by the memory controller, the plurality of registers including a first register to store a first value representative of a drive strength setting of an output driver, the first value to be provided by the memory controller in connection with the access request; and,
a transmitter circuit to output data to the memory controller device, the transmitter circuit including the output driver to output the data using the drive strength setting.
2. The system of claim 1 , wherein the first value is derived by the memory controller device based on a count of memory devices coupled to the memory controller device via a bus.
3. The system of claim 1 , wherein the drive strength setting of the output driver can be set to at least three different values.
4. The system of claim 1 , further comprising:
a second register to store a second value representative of at least one transmission parameter, the second value being received from the memory controller device.
5. The system of claim 4 , wherein variations of the second value result in variations of a slew rate of the output driver.
6. The system of claim 5 , wherein the memory controller derives the second value based on a topology of memory devices coupled to the memory controller device via a bus.
7. The system of claim 4 , wherein the second value affects at least one of transmit timing, slew rate, duty cycle, and equalization, of the output driver.
8. A method of operation in a system, the method comprising:
a controller device transmitting, over a bidirectional bus, information representing at least one parameter for data transfer;
receiving the information at a port of a flash device;
storing the information in a register on the flash device; and
setting, by the flash device, a transmission parameter of an output signal driven onto the bidirectional bus by an output driver, the transmission parameter of the output signal being set in accordance with parameter control signal that is adjusted based on the information.
9. The method of claim 8 , wherein the information is based on a count of memory devices on the bidirectional bus.
10. The method of claim 8 , wherein the transmission parameter corresponds to a drive strength.
11. The method of claim 10 , wherein at least three different values may be selected as the drive strength.
12. The method of claim 8 , wherein the transmission parameter affects a slew rate of the output signal.
13. The method of claim 8 , wherein the transmission parameter of the output signal is at least one of drive strength, transmit timing, slew rate, and equalization.
14. The method of claim 8 , wherein the information is based on a topology of memory devices disposed on the bidirectional bus.
15. A system comprising:
a memory controller device coupled to a bus; and
a plurality of flash memory devices coupled to the bus, each flash device of the plurality of flash devices comprising:
a bidirectional port to receive a parameter control value corresponding to a feature of a particular flash device of the plurality of flash devices;
a register, coupled to the bidirectional port, to store the parameter control value; and
an output driver to drive data in accordance with a transmission parameter determined by the parameter control value, the output driver to drive the data onto the bus via the bidirectional port.
16. The system of claim 15 , wherein the parameter control value of each flash device of the plurality of flash devices is to be set in accordance with a count of flash memory devices on the bus.
17. The system of claim 15 , wherein the transmission parameter of each flash device of the plurality of flash devices corresponds to a selected drive strength.
18. The system of claim 17 , wherein at least three different values may be selected as the selected drive strength.
19. The system of claim 15 , wherein the transmission parameter of each flash device of the plurality of flash devices affects a slew rate of a corresponding output driver of each flash device of the plurality of flash devices.
20. The system of claim 15 , wherein the parameter control value of each flash device of the plurality of flash devices is to be selected based on a topology of the plurality of flash memory devices.
21. A system comprising:
a memory controller device; and
a flash memory device coupled to the memory controller device via a port on the flash memory device, the flash memory device comprising:
means for driving data to the memory controller device via the port; and
means for storing a first value representative of a drive strength setting for the driving of the data, the first value to be received from the memory controller device via the port.