Structure and method for biasing phase change memory array for reliable writing
View Patent ↗A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material.
1. A method of programming a non-volatile memory array, the method comprising:
providing a plurality of memory cells in the non-volatile memory array, each of the memory cells comprising a reversibly switchable material formed in series with a dielectric material, a non-ohmic element and a resistive heater,
supplying a first programming current to a first memory cell, wherein the first programming current is generated by a programmable control circuit and applied at an intermediate level for a long duration such that the first memory cell is programmed into a set state; and
supplying a second programming current to a second memory cell, wherein the second programming current is generated by the programmable control circuit and applied at a high level for a short duration such that the second memory cell is programmed into a reset state, supplying of said second programming current simultaneous with supplying of said first programming current.
2. The method of claim 1 , wherein said dielectric material of said first memory cell comprises a low-resistance rupture region.
3. The method of claim 1 , further comprising:
supplying a first programming pulse to said first memory cell when said first programming current is supplied; and
supplying a second programming pulse to said second memory cell when said second programming current is supplied, said first programming pulse being longer in duration than said second programming pulse.
4. The method of claim 3 , wherein said first programming pulse and said second programming pulse begin at substantially the same time.
5. The method of claim 1 , wherein said non-ohmic element comprises a diode.
6. A method of programming a memory chip, the method comprising:
providing a first programming pulse to a first memory cell, said first programming pulse comprising a current amplitude sufficient to program said first memory cell into a set state, said first programming pulse is generated using a self-timed programmable pulse width control circuit, said first memory cell comprising a switchable memory material in series with an anti-fuse and a diode; and
providing a second programming pulse to a second memory cell, said second programming pulse comprising a current amplitude sufficient to program said second memory cell into a reset state, said second memory cell comprising a switchable memory material in series with an anti-fuse and a diode, said second programming pulse overlapping in time with said first programming pulse.
7. The method of claim 6 , wherein said first programming pulse is wider than second programming pulse.
8. The method of claim 7 , wherein said switchable memory material of said first memory cell is a chalcogenide material.
9. The method of claim 8 , wherein said anti-fuse of said second memory cell comprises silicon dioxide.
10. The method of claim 6 , wherein said programmable pulse width control circuit comprises a string of inverters.
11. The method of claim 6 , wherein said anti-fuse of said second memory cell is ruptured.
12. The method of claim 6 , wherein each of said first and second memory cells further comprises a heater in series with the switchable memory material, the anti-fuse and the diode.
13. The method of claim 12 , wherein said second memory cell is a two-terminal memory cell.
14. A method of writing two-terminal non-volatile memory cells, the method comprising:
programming a first memory cell into a set state using a first programming pulse, said first memory cell comprising a dielectric layer in series with a phase change material and a non-ohmic conductive device, said first programmable pulse is generated using a programmable pulse width control circuit, wherein said programmable pulse width circuit and said first memory cell share a semiconductor substrate; and
programming a second memory cell into a reset state using a second programming pulse, said second memory cell comprising a dielectric layer in series with a phase change material and a non-ohmic conductive device, wherein said first memory cell and said second memory cell are programmed simultaneously.
15. The method of claim 14 , wherein said first programming pulse is wider than said second programming pulse.
16. The method of claim 15 , further comprising:
coupling a first current mirror to said first memory cell; and
coupling a second current mirror to said second memory cell, said second current mirror providing a larger current than said first current mirror.
17. The method of claim 14 , wherein each of said first and second memory cells further comprises a heater in series with the dielectric material, the phase change element and the non-ohmic conductive device.
18. The method of claim 14 , wherein said non-ohmic conductive device comprises a diode.
19. The method of claim 18 , wherein said phase change material of said first memory cell is a chalcogenide material.
20. The method of claim 19 , wherein said dielectric layer of said first memory cell forms a low-resistance rupture region.