IP Library Granted Patent US 7,659,576
Granted Patent B2
US 7,659,576 · App. 11/933,897 · Granted Feb 9, 2010

Semiconductor device and method of manufacturing the same

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,659,576
App. No.
11/933,897
Granted
Feb 9, 2010
Kind
B2
Abstract

A punch-through type IGBT generally has a thick p ++ -type collector layer. Therefore, the FWD need be externally attached to the IGBT when the IGBT is used as a switching element in an inverter circuit for driving a motor load, and thus the number of processes and components increases. In the invention, trenches are formed penetrating through a collector layer and reaching a buffer layer. A collector electrode is formed in the trenches, too. With this structure, a current path is formed between an emitter electrode and the collector electrode without through the collector layer and functions as the FWD.

Claims (33)

1. A semiconductor device comprising:

a collector layer of a first general conductivity type;

a drift layer of a second general conductivity type disposed on a front surface of the collector layer;

a base layer of the first general conductivity type disposed on the drift layer;

a first trench penetrating through the base layer so as to reach the drift layer

a second trench penetrating through the base layer so as to reach the drift layer;

a gate insulation film disposed on an inner wall of each of the first and second trenches;

a gate electrode disposed in each of the first and second trenches so as to cover the gate insulation film;

an emitter region of the second general conductivity type formed, for each of the first and second trenches, in the base layer and adjacent a corresponding trench;

an emitter electrode connected to the emitter regions; and

a collector electrode disposed on a back surface of the collector layer and comprising branching portions penetrating through the collector layer,

wherein one of the branching portions is disposed under the base layer between the first trench and the second trench, and

none of the branching portions is disposed under the first trench or the second trench.

2. The semiconductor device of claim 1 , further comprising a buffer layer of the second general conductivity type disposed between the collector layer and the drift layer and having a higher impurity concentration than the drift layer.

3. The semiconductor device of claim 2 , wherein the branching portions terminate in the buffer layer.

4. The semiconductor device of claim 1 , wherein the branching portions are formed as trenches.

5. The semiconductor device of claim 4 , wherein the collector electrode fills the trenches.

6. The semiconductor device of claim 1 , wherein the branching portions comprise tapered sidewalls.

7. The semiconductor device of claim 1 , wherein the collector electrode comprises copper.

8. The semiconductor device of claim 1 , wherein the collector electrode comprises polysilicon.

9. A method of manufacturing a semiconductor device, comprising:

providing a collector layer of a first general conductivity type;

forming a drift layer of a second general conductivity type on a front surface of the collector layer;

forming a base layer of the first general conductivity type on the drift layer;

forming trenches penetrating through the base layer so as to reach the drift layer;

forming a gate insulation film on an inner wall of each of the trenches;

forming a gate electrode in each of the trenches so as to cover a corresponding gate insulation film;

forming emitter regions of the second general conductivity type in the base layer and adjacent the trenches;

forming an emitter electrode connected to the emitter regions;

forming openings from a back surface of the collector layer so that the openings penetrate through the collector layer; and

forming a collector electrode on the back surface of the collector layer so as to fill the openings at least partially,

wherein the openings are formed under base layer between the trenches, and

no openings are formed under the trenches.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 033813 FRAME: 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jan 21, 2015
From: SYSTEM SOLUTIONS CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 034816/0510 →
CHANGE OF NAME Recorded Dec 3, 2014
From: SANYO SEMICONDUCTOR CO., LTD
To: SYSTEM SOLUTIONS CO., LTD.
Reel/Frame 034537/0044 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2014
From: SANYO SEMICONDUCTOR CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033813/0420 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2014
From: SANYO ELECTRIC CO., LTD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 032836/0342 →