Semiconductor device and method of forming the same
View Patent ↗A semiconductor device includes a semiconductor substrate, source and drain regions on the semiconductor substrate, and contact plugs connected to the source and drain regions. The contact plugs includes first impurity-diffused epitaxial layers that contact with the source and drain regions.
1. A method of forming a MOS transistor in an active region surrounded by an isolation film, the method comprising:
forming a gate insulating film on a first part of the active region;
forming a gate electrode on the gate insulating film;
forming diffusion layers in second parts of the active region, the second parts being different from the first part;
forming first silicon layers on the diffusion layers by selective epitaxial method to form source and drain regions which comprise stacks of the first silicon layers and the diffusion layers;
forming an inter-layer insulator which covers the gate electrode and the source and drain regions;
forming contact holes in the inter-layer insulator, the contact holes reaching the source and drain regions;
forming second silicon layers in the contact holes, the second silicon layers contacting with the source and drain regions; wherein a second impurity is introduced into the second silicon layers, and the second impurity is diffused to the first silicon layer.
2. The method according to claim 1 , wherein a first impurity is introduced into the first silicon layers before forming an inter-layer insulator which covers the gate electrode and the source and drain regions.
3. The method according to claim 1 , wherein the second silicon layer is formed by selective epitaxial method.
4. The method according to claim 3 , wherein the impurity is introduced by ion implantation from a top surface of the second silicon layer.
5. The method according to claim 1 , wherein the second silicon layer is formed by depositing a phosphorous-doped silicon layer and removing a part of the phosphorous-doped silicon layer to form a contact plug.
6. The method according to claim 1 , wherein the level of a top surface of the second silicon layers is lower than the level of a top surface of the inter-layer insulator.
7. The method according to claim 6 , further comprising: forming a metal layer on the second silicon layers and the inter-layer insulator; and
removing a part of the metal layer by chemical mechanical polishing method, while having the metal layer remain in the contact holes.