Delay fault test quality calculation apparatus, delay fault test quality calculation method, and delay fault test pattern generation apparatus

1. A delay fault test quality calculation apparatus for calculating delay fault test quality to be achieved by a test pattern to be applied to a semiconductor integrated circuit, comprising:

a defect distribution extraction unit which extracts a distribution of resistance or current caused by physical defects related to layout elements or a combination of the layout elements composing the semiconductor integrated circuit;

a delay fault-layout element information extraction unit which extracts the layout elements or the combination of the layout elements with interconnect wiring information including location information and interconnect capacitance, and a delay fault to be associated with inside the semiconductor integrated circuit as delay fault-layout element information by associating the layout elements or the combination thereof with delay faults to be assumed inside the semiconductor integrated circuit, the delay fault resulting from a value obtained from the resistance and interconnect capacitance of the layout element, or the combination thereof;

a delay defect distribution calculation and weighting unit which calculates a distribution of delay defect on the basis of the distribution of the resistance or current and adds weight to each of the delay faults on the basis of the delay fault-layout element information; and

a delay fault test quality calculation unit which calculates the delay fault test quality on the basis of delay design information of the semiconductor integrated circuit, detection information of the test pattern to test the semiconductor integrated circuit, execution conditions of the test, the delay defect distribution of resistance or current caused by physical defects, and the weights.

2. The delay fault test quality calculation apparatus according to claim 1 , wherein

the delay defect distribution calculation and weighting unit obtains a distribution of delay defect cause by a distribution of resistance caused by physical defects of VIAs to each delay fault by using a resistance into delay conversion formula.

3. The delay fault test quality calculation apparatus according to claim 2 , wherein

the resistance into delay conversion formula is expressed by an equation as follows:

D ( i,k {j} ,R )= C ( i,k {j} ,R )×fLOC( i,k {j} )× R

[VIAk on net (i)]

[{j}=(partial) aggregate of delay faults assumed at a connection destination basic cell input terminals (j) of net (i)]

wherein, fLOC is detailed position information of each VIA inside an LSI logical net (i), D is a delay on net i resulting from 1) resistance R of VIAk (k refers to one of VIAs on net i), assigned to each of the delay faults {j} affected by the resistance R among those assumed at destination cell input terminals (i), and 2) the load capacitance C from an output terminal of driving cell of net I through VIAk to each of the destination cell input terminals and 3) the detailed position information fLOC of VIAk on net i.

4. The delay fault test quality calculation apparatus according to claim 1 , wherein

the delay fault test quality calculation unit calculates the delay fault test quality by an equation expressed as follows:

DL ( i )=∫ Tmgn(i) Tdet(i) F ( D ) dD

[delay fault test quality of (input) fault i]

DL

⁡

(

LSI

)

=

∑

i

⁢

DL

⁡

(

i

)

(delay fault test quality of whole of semiconductor integrated circuit)

wherein, F(D) is the delay defect distribution, Tmgn(i) is delay design information of the semiconductor integrated circuit, Tdet(i) is detection information of the test pattern.

5. The delay fault test quality calculation apparatus according to claim 1 , wherein

the physical defect distribution is continuously obtained by measuring test element groups for evaluation at shipment tests of products, and by accumulating the measurement results.

6. A delay fault test quality calculation method for calculating delay fault test quality to be achieved by a test pattern to be applied to a semiconductor integrated circuit, comprising:

extracting a distribution of resistances or currents caused by physical defects related to layout elements or a combination of the layout elements composing the semiconductor integrated circuit by using a computer;

extracting interconnected wiring information including location information and interconnect capacitance, and a delay fault to be associated with the layout elements or the combination of the layout elements inside the semiconductor integrated circuit as delay fault-layout element information by associating the layout elements or the combination thereof with delay faults to be assumed inside the semiconductor integrated circuit, the delay fault resulting from a value obtained from the resistance and interconnect capacitance of the layout element or a combination thereof;

calculating a distribution of delay defect on the basis of the distribution of the resistance or current and adding weight to each of the delay defaults on the basis of the delay fault-layout element information; and

calculating the delay fault test quality on the basis of delay design information of the semiconductor integrated circuit, detection information of the test pattern to test the semiconductor integrated circuit, execution conditions of the test, the distribution of resistances or currents cause by physical defects, and the weights.

7. The delay fault test quality calculation method, according to claim 6 , wherein

the calculating of the delay defect obtains of VIAs to each delay fault by using a resistance into delay conversion formula.

8. The delay fault test quality calculation method according to claim 7 , wherein the resistance into delay conversion formula is expressed in an equation as follows:

D ( i,k {j} ,R )= C ( i,k {j} ,R )×fLOC( i,k {j} )× R ( VIAk on net ( i))

[{j}=(partial) aggregate of delay faults assumed at a connection destination basic cell input terminals (j) of net (i)]

wherein, fLOC is detailed position information of each VIA inside an LSI logical net (i), D is a delay on net i resulting from 1) resistance R of VIAk (k refers to one of VIAs on net i), assigned to each of the delay faults {j} affected by the resistance R among those assumed at destination cell input terminals (i), and 2) the load capacitance C from an output terminal of driving cell of net I through VIAk to each of the destination cell input terminals and 3) the detailed position information fLOC of VIAk on net i.

9. The delay fault test quality calculation method according to claim 6 , wherein

the calculating of the delay fault test quality calculates the delay fault test quality by an equation expressed as follows:

DL ( i )=∫ Tmgn(i) Tdet(i) F ( D ) dD

[delay fault test quality of (input) fault i]

DL

⁡

(

LSI

)

=

∑

i

⁢

DL

⁡

(

i

)

(delay fault test quality of whole of semiconductor integrated circuit)

wherein, F(D) is the delay defect distribution, Tmgn(i) is delay design information of the semiconductor integrated circuit, Tdet(i) is detection information of the test pattern.

10. The delay fault test quality calculation method according to claim 6 , wherein

the physical defect distribution is continuously obtained by measuring test element groups for evaluation at shipment tests of products, and by accumulating the measurement results.

11. The delay fault quality calculation apparatus according to claim 1 , wherein

the delay defect calculation unit obtains a distribution of delay defect caused by a a distribution of resistance caused by physical defects on interconnect to each delay fault by using a resistance into delay conversion formula.