Patent Assignment
Reel/Frame 022248/0521
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2009-02-13
Received: 2009-02-13
Pages: 10
Assignor
FUJITSU LIMITED
Executed: 2009-01-23
Assignee
FUJITSU MICROELECTRONICS LIMITED
7-1, NISHI-SHINJUKU 2-CHOME, SHINJUKU-KU, TOKYO, JPX, 163-0722, JAPAN
Covered Applications
(69)
ANTENNA APPARATUS UTILIZING APERTURE OF TRANSMISSION LINE
App. No. 12/155,247
→
MANUFACTURING METHOD FOR FERROELECTRIC MEMORY DEVICE
App. No. 11/998,177
→
MANUFACTURING METHOD FOR FERROELECTRIC MEMORY DEVICE
App. No. 11/998,176
→
DELAY FAULT TEST QUALITY CALCULATION APPARATUS, DELAY FAULT TEST QUALITY CALCULATION METHOD, AND DELAY FAULT TEST PATTERN GENERATION APPARATUS
App. No. 11/943,170
→
GATEWAY APPARATUS AND DATA TRANSFER CONTROL METHOD
App. No. 11/976,687
→
GATEWAY APPARATUS AND DATA MANAGING METHOD
App. No. 11/976,546
→
ERROR DETECTOR AND ERROR DETECTION METHOD
App. No. 11/976,544
→
SEMICONDUCTOR DEVICE AND PROCESS FOR MANUFACTURING THE SAME
App. No. 11/889,100
→
SEMICONDUCTOR DEVICE WITH VIA HOLE OF UNEVEN WIDTH
App. No. 11/808,667
→
SUBSTRATE PROCESSING METHOD AND APPARATUS FABRICATION PROCESS OF A SEMICONDUCTOR DEVICE
App. No. 11/687,738
→
Method for fabricating a semiconductor device
App. No. 11/699,984
→
Scheduling in a multicore processor
App. No. 11/540,146
→
MANAGING POWER CONSUMPTION IN A MULTICORE PROCESSOR
App. No. 11/541,315
→
NARROW IMPEDANCE CONVERSION DEVICE
App. No. 11/500,943
→
Method of forming semiconductor layer
App. No. 11/491,300
→
METHOD FOR DESIGNING A SEMICONDUCTOR INTEGRATED CIRCUIT LAYOUT CAPABLE OF REDUCING THE PROCESSING TIME FOR OPTICAL PROXIMITY EFFECT CORRECTION
App. No. 11/486,107
→
METHOD OF MANUFACTURING WIRING SUBSTRATE HAVING TERMINATED BUSES
App. No. 11/440,113
→
GATEWAY APPARATUS AND ROUTING METHOD
App. No. 11/412,048
→
SEMICONDUCTOR MEMORY DEVICE
App. No. 11/360,681
→
SEMICONDUCTOR DEVICE AND PROCESS FOR MANUFACTURING THE SAME
App. No. 11/213,882
→
HIGH-RELIABLE SEMICONDUCTOR DEVICE USING HERMETIC SEALING OF ELECTRODES
App. No. 11/212,912
→
MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
App. No. 11/182,024
→
A DEVICE FOR BONDING A METAL ON A SURFACE OF A SUBSTRATE
App. No. 10/528,690
→
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE DEVICE
App. No. 11/077,212
→
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
App. No. 11/055,707
→
Flat-object holder and method of using the same
App. No. 10/985,949
→
DEBUG IN A MULTICORE ARCHITECTURE
App. No. 10/941,457
→
METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE
App. No. 10/924,847
→
SIGNAL TRANSMISSION SYSTEM, AND SIGNAL TRANSMISSION LINE
App. No. 10/898,874
→
SEMICONDUCTOR DEVICE WITH TRANSISTOR AND CAPACITOR AND ITS MANUFACTURE METHOD
App. No. 10/845,153
→
METHOD OF MOUNTING AN ELECTRONIC PART
App. No. 10/828,210
→
RESOURCE MANAGEMENT IN A MULTICORE ARCHITECTURE
App. No. 10/816,328
→
ELECTRONIC CIRCUIT DEVICE
App. No. 10/781,942
→
SIGNAL TRANSMISSION APPARATUS AND INTERCONNECTION STRUCTURE
App. No. 10/775,223
→
CLEANING GAS AND ETCHING GAS
App. No. 10/480,285
→
METHOD OF RESIN ENCAPSULATION, APPARATUS FOR RESIN ENCAPSULATION, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE AND RESIN MATERIAL
App. No. 10/719,379
→
METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE
App. No. 10/705,881
→
CAPACITOR
App. No. 10/705,889
→
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
App. No. 10/603,982
→
SEMICONDUCTOR DEVICE WITH REDUCED PARASITIC CAPACITANCE BETWEEN IMPURITY DIFFUSION REGIONS
App. No. 10/393,389
→
SURFACE INSPECTION METHOD AND SURFACE INSPECTION SYSTEM
App. No. 10/393,833
→
METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING LOW DIELECTRIC CONSTANT INSULATOR FILM
App. No. 10/391,022
→
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE DEVICE
App. No. 10/391,889
→
SEMICONDUCTOR DEVICE WITH BUILT-IN LIGHT RECEIVING ELEMENT, PRODUCTION METHOD THEREOF, AND OPTICAL PICKUP INCORPORATING THE SAME
App. No. 10/384,774
→
SEMICONDUCTOR DEVICE MANUFACTURING METHOD
App. No. 10/372,275
→
SIGNAL TRANSMISSION SYSTEM
App. No. 10/353,040
→
SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
App. No. 10/350,420
→
CIRCUIT STRUCTURE AND SEMICONDUCTOR INTEGRATED CIRCUIT
App. No. 10/348,896
→
ELECTRONIC DEVICE
App. No. 10/331,767
→
SEMICONDUCTOR DEVICE WITH TRANSISTOR AND CAPACITOR AND ITS MANUFACTURE METHOD
App. No. 10/317,063
→
WIRING SUBSTRATE
App. No. 10/228,305
→
FLAT-OBJECT HOLDER AND METHOD OF USING THE SAME
App. No. 10/208,104
→
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
App. No. 10/195,484
→
CAPACITOR
App. No. 10/173,596
→
SEMICONDUCTOR MEMORY DEVICE WITH REDUCED ITS CHIP AREA AND POWER CONSUMPTION
App. No. 10/103,141
→
METHOD OF TERMINATING BUS, BUS TERMINATION RESISTOR, AND WIRING SUBSTRATE HAVING TERMINATED BUSES AND METHOD OF ITS MANUFACTURE
App. No. 10/079,464
→
ALIGNMENT SENSING METHOD FOR SEMICONDUCTOR DEVICE
App. No. 10/073,314
→
DIGITAL-TO-ANALOG CONVERTER AND SYNCHRONOUS CIRCUIT USING THE CONVERTER
App. No. 10/007,694
→
METHOD FOR MANUFACTURING AN INTERCONNECT STRUCTURE FOR STACKED SEMICONDUCTOR DEVICE
App. No. 09/997,878
→
WIRING STRUCTURE FOR TRANSMISSION LINE HAVING GROOVED CONDUCTORS
App. No. 09/988,017
→
A SEMICONDUCTOR INTERGRATED CIRCUIT HAVING SWITCHING TRANSISTORS AND VARACTORS
App. No. 09/963,500
→
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
App. No. 09/939,639
→
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
App. No. 09/928,489
→
SEMICONDUCTOR CIRCUIT DEVICE HAVING POWER AND GROUND LINES ADAPTED FOR HIGH-FREQUENCY OPERATION
App. No. 09/900,960
→
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE DEVICE
App. No. 09/898,082
→
SEMICONDUCTOR DEVICE
App. No. 09/898,033
→
SEMICONDUCTOR MEMORY DEVICE HAVING SEGMENT TYPE WORD LINE STRUCTURE
App. No. 09/871,646
→
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
App. No. 09/779,531
→
DRIVER CIRCUIT, RECEIVER CIRCUIT, AND SIGNAL TRANSMISSION BUS SYSTEM
App. No. 09/761,583
→