IP Library Granted Patent US 7,116,184
Granted Patent B2
US 7,116,184 · App. 10/079,464 · Granted Oct 3, 2006

Method of terminating bus, bus termination resistor, and wiring substrate having terminated buses and method of its manufacture

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Quick Facts
Patent No.
US 7,116,184
App. No.
10/079,464
Granted
Oct 3, 2006
Kind
B2
Abstract

A terminal resistor is provided at the end of a bus formed on a wiring substrate. An insulator having a large dielectric loss angle is provided in the vicinity of the terminal resistor to absorb high frequency electromagnetic waves in the vicinity. This arrangement permits successful transmission of digital signals in the GHz region using a conventional terminal resistor.

Claims (80)

1. A wiring substrate, comprising:

an insulative substrate;

a multiplicity of paired transmission lines formed on said insulative substrate;

terminal chip resistors connected between the terminal ends of the respective paired transmission lines;

insulators each formed to cover one terminal resistor, said insulator having a larger dielectric loss angle than said insulative substrate at least in the frequency range of digital signals to be transmitted,

wherein each of said insulators is a thermosetting organic material containing a hydroxyl radical.

2. A wiring substrate, comprising:

an insulative substrate;

a multiplicity of paired transmission lines formed on said insulative substrate;

terminal chip resistors connected between the terminal ends of the respective paired transmission lines;

insulators each formed to cover one terminal resistor, said insulator having a larger dielectric loss angle than said insulative substrate at least in the frequency range of digital signals to be transmitted,

wherein each of said insulators is a mixture of glass powder containing a modified ionized additive and a thermosetting organic material containing a hydroxyl radical.

3. A wiring substrate, comprising:

an insulative substrate;

a multiplicity of paired transmission lines formed on said insulative substrate;

terminal chip resistors connected between the terminal ends of the respective paired transmission lines;

insulators each formed to cover one terminal resistor, said insulator having a larger dielectric loss angle than said insulative substrate at least in the frequency range of digital signals to be transmitted,

wherein each of said terminal resistors comprises:

a glass substrate containing a modified ionized additive and having a dielectric loss angle which is greater than that of said wiring substrate;

a resistive film formed on one surface of said glass substrate; and

a pair of electrodes formed on the opposite ends of said resistive film.

4. A wiring substrate, comprising:

an insulative substrate including predetermined regions which have a larger dielectric loss angle at least in the frequency region of pulse signals transmitted than the rest regions of said insulative substrate;

paired transmission lines having terminal ends in said respective predetermined regions of said insulative substrate;

terminal chip resistors each connected between the terminal ends of respective paired transmission lines,

wherein each of said regions of said insulative substrate having said large dielectric loss angle is formed of a thermosetting organic material containing a hydroxyl radical.

5. The wiring substrate according to claim 4 , wherein each of said predetermined regions of said insulative substrate extends to the terminal sections of respective paired transmission lines.

6. A wiring substrate, comprising:

an insulative substrate including predetermined regions which have a larger dielectric loss angle at least in the frequency region of pulse signals transmitted than the rest regions of said insulative substrate;

paired transmission lines having terminal ends in said respective predetermined regions of said insulative substrate;

terminal chip resistors each connected between the terminal ends of respective paired transmission lines,

wherein each of said regions of said insulative substrate having said large dielectric loss angle is formed of a mixture of glass powder containing at least a modified ionized additive and an organic thermosetting material containing a hydroxyl radical.

7. The wiring substrate according to claim 6 , wherein each of said predetermined regions of said insulative substrate extends to the terminal sections of respective paired transmission lines.

8. A wiring substrate, comprising:

an insulative substrate including predetermined regions which have a larger dielectric loss angle at least in the frequency region of pulse signals transmitted than the rest regions of said insulative substrate;

paired transmission lines having terminal ends in said respective predetermined regions of said insulative substrate;

terminal chip resistors each connected between the terminal ends of respective paired transmission lines,

wherein each of said terminal resistors comprises:

a glass substrate containing a modified ionized additive and having a dielectric loss angle which is greater than that of said wiring substrate;

a resistive film formed on one surface of said glass substrate; and

a pair of electrodes formed on the opposite ends of said resistive film.

9. The wiring substrate according to claim 8 , wherein each of said predetermined regions of said insulative substrate extends to the terminal sections of respective paired transmission lines.

10. A wiring substrate, comprising:

an insulative substrate;

a multiplicity of paired transmission lines formed on said insulative substrate;

terminal chip resistors each connected between the terminal ends of the respective paired transmission lines; and

insulators formed to cover the respective terminal resistors and the terminal sections of said paired transmission lines connected with said terminal resistors, said insulators being made of a mixture of a magnetic material and an organic resin.

11. The wiring substrate according to claim 10 , wherein said magnetic material is a material that exhibits ferri-magnetic resonance.

12. A wiring substrate, comprising:

an insulative substrate having insulative members which are formed at predetermined regions thereof and made of a mixture of a magnetic material and an organic resin;

paired transmission lines having their terminal ends positioned in said predetermined sections of said insulative substrate; and

terminal chip resistors each connected between the terminal ends of the respective paired transmission lines.

13. The wiring substrate according to claim 12 , wherein said magnetic material is a material that exhibits ferri-magnetic resonance.

14. A wiring substrate, comprising:

an insulative substrate;

a multiplicity of paired transmission lines formed on said insulative substrate;

terminal chip resistors connected between the terminal ends of the respective paired transmission lines;

insulators each formed to cover a respective terminal resistor and terminal ends of respective paired transmission lines, said insulator having a larger dielectric loss angle than said insulative substrate at least in the frequency range of digital signals transmitted by said transmission lines,

wherein each of said insulators is a thermosetting organic material containing a hydroxyl radical.

15. A wiring substrate, comprising:

an insulative substrate;

a multiplicity of paired transmission lines formed on said insulative substrate;

terminal chip resistors connected between the terminal ends of the respective paired transmission lines;

insulators each formed to cover a respective terminal resistor and terminal ends of respective paired transmission lines, said insulator having a larger dielectric loss angle than said insulative substrate at least in the frequency range of digital signals transmitted by said transmission lines,

wherein each of said insulators is a mixture of glass powder containing a modified ionized additive and a thermosetting organic material containing a hydroxyl radical.

16. A wiring substrate, comprising:

an insulative substrate;

a multiplicity of paired transmission lines formed on said insulative substrate;

terminal chip resistors connected between the terminal ends of the respective paired transmission lines;

insulators each formed to cover a respective terminal resistor and terminal ends of respective paired transmission lines, said insulator having a larger dielectric loss angle than said insulative substrate at least in the frequency range of digital signals transmitted by said transmission lines,

wherein each of said terminal resistors comprises:

a glass substrate containing a modified ionized additive and having a dielectric loss angle which is greater than that of said wiring substrate;

a resistive film formed on one surface of said glass substrate; and

a pair of electrodes formed on the opposite ends of said resistive film.

17. A method of terminating a bus, comprising steps of:

connecting a chip type terminal resistor to one end of a bus formed on an insulative substrate for transmitting a digital signal;

providing in the vicinity of said terminal resistor an insulator having a larger dielectric loss angle at least in the frequency region of said digital signal than said insulative substrate, wherein

said insulator is adapted to absorb and dissipate high frequency electromagnetic energy of high harmonic frequency components of said digital signal and of apparent high frequency components associated with transition time, said high frequency electromagnetic energy entering said bus and reaching said one end,

wherein said insulator includes a thermosetting organic material containing a hydroxyl radical.

18. The method of terminating a bus according to claim 17 , wherein said insulator includes a glass material which contains a modified ionized additive.

Assignments (19)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2021
From: PANASONIC CORPORATION
To: NUVOTON TECHNOLOGY CORPORATION JAPAN
Reel/Frame 055502/0185 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME ADDRESS PREVIOUSLY RECORDED AT REEL: 028986 FRAME: 0564. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 31, 2019
From: SHARP KABUSHIKI KAISHA
To: OTSUKA, KANJI; USAMI, TAMOTSU; ROHM CO., LTD; SANYO ELECTRIC CO., LTD.; SONY CORPORATION; KABUSHIKI KAISHA TOSHIBA; NEC CORPORATION; RENESAS ELECTRONICS CORPORATION; PANASONIC CORPORATION; FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 049334/0316 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EIGHTH ASSIGNEE NAME AND ADDRESS PREVIOUSLY RECORDED AT REEL: 031174 FRAME: 0452. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jan 19, 2018
From: LAPIS SEMICONDUCTOR CO., LTD.
To: OTSUKA, KANJI; USAMI, TAMOTSU; ROHM CO., LTD; SANYO ELECTRIC CO., LTD.; SONY CORPORATION; KABUSHIKI KAISHA TOSHIBA; NEC CORPORATION; RENESAS ELECTRONICS CORPORATION; PANASONIC CORPORATION; FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 045095/0561 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME AND THE ADDRESS PREVIOUSLY RECORDED ON REEL 044070 FRAME 0960. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jan 19, 2018
From: NEC CORPORATION; FUJITSU SEMICONDUCTOR LIMITED
To: OTSUKA, KANJI; USAMI, TAMOTSU; ROHM CO., LTD.; SANYO ELECTRIC CO., LTD.; KABUSHIKI KAISHA TOSHIBA; RENESAS ELECTRONICS CORPORATION; PANASONIC CORPORATION
Reel/Frame 045096/0617 →
CORRECTIVE ASSIGNMENT TO CORRECT THE SEVENTH ASSIGNEE'S NAME AND ADDRESS PREVIOUSLY RECORDED AT REEL: 033487 FRAME: 0476. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jan 19, 2018
From: SONY CORPORATION
To: OTSUKA, KANJI; USAMI, TAMOTSU; ROHM CO., LTD.; SANYO ELECTRIC CO., LTD.; KABUSHIKI KAISHA TOSHIBA; NEC CORPORATION; RENESAS ELECTRONICS CORPORATION; PANASONIC CORPORATION; FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 045167/0005 →
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 29, 2017
From: NEC CORPORATION; FUJITSU SEMICONDUCTOR LIMITED
To: OTSUKA, KANJI; USAMI, TAMOTSU; ROHM CO., LTD.; SANYO ELECTRIC CO., LTD.; KABUSHIKI KAISHA TOSHIBA; RENESAS TECHNOLOGY CORP.; PANASONIC CORPORATION
Reel/Frame 044070/0960 →
CHANGE OF ADDRESS Recorded Jul 21, 2017
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 043289/0749 →
MERGER AND CHANGE OF NAME Recorded Sep 9, 2014
From: RENESAS TECHNOLOGY CORP.; NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 033698/0648 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 7, 2014
From: SONY CORPORATION
To: OTSUKA, KANJI; USAMI, TAMOTSU; ROHM CO., LTD.; SANYO ELECTRIC CO., LTD.; KABUSHIKI KAISHA TOSHIBA; NEC CORPORATION; RENESAS TECHNOLOGY CORP.; PANASONIC CORPORATION; FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 033487/0476 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 10, 2013
From: LAPIS SEMICONDUCTOR CO., LTD.
To: OTSUKA, KANJI; USAMI, TAMOTSU; ROHM CO., LTD; SANYO ELECTRIC CO., LTD; SONY CORPORATION; KABUSHIKI KAISHA TOSHIBA; NEC CORPORATION; RENESAS TECHNOLOGY CORP.; PANASONIC CORPORATION; FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 031174/0452 →
CHANGE OF NAME Recorded Aug 30, 2013
From: OKI SEMICONDUCTOR CO., LTD.
To: LAPIS SEMICONDUCTOR CO., LTD.
Reel/Frame 031125/0334 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 19, 2012
From: SHARP KABUSHIKI KAISHA
To: OTSUKA, KANJI; USAMI, TAMOTSU; ROHM CO., LTD; SANYO ELECTRIC CO., LTD; SONY CORPORATION; KABUSHIKI KAISHA TOSHIBA; NEC CORPORATION; RENESAS TECHNOLOGY CORP.; PANASONIC CORPORATION; OKI SEMICONDUCTOR CO., LTD.; FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 028986/0564 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 6, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024794/0802 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2009
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 022248/0521 →
CHANGE OF NAME Recorded Dec 11, 2008
From: OKI ELECTRIC INDUSTRY CO., LTD.
To: OKI SEMICONDUCTOR CO., LTD.
Reel/Frame 022052/0540 →
CHANGE OF NAME Recorded Nov 20, 2008
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 021894/0636 →
CHANGE OF ASSIGNEE Recorded Oct 25, 2005
From: HITACHI, LTD.; MITSUBISHI DENKI KABUSHIKI KAISHA
To: RENESAS TECHNOLOGY CORP.
Reel/Frame 016681/0484 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2002
From: OTSUKA, KANJI; USAMI, TAMOTSU
To: OTSUKA, KANJI; USAMI, TAMOTSU; ROHM CO., LTD; OKI ELECTRIC INDUSTRY CO., LTD; SANYO ELECTRIC CO., LTD; SONY CORPORATION; KABUSHIKI KAISHA TOSHIBA; NEC CORPORATION; SHARP KABUSHIKI KAISHA; HITACHI, LTD; FUJITSU LIMITED; MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD; MITSUBISHI DENKI KABUSHIKI KAISHA
Reel/Frame 012954/0686 →