Method for reducing charge loss in analog floating gate cell

1. A method of providing a reference voltage in an integrated circuit, comprising:

programming a threshold voltage of a first non-volatile memory (NVM) transistor via a tunneling capacitor, wherein the first NVM transistor and the tunneling capacitor share a first floating gate and the tunneling capacitor has a programming terminal separate from the first floating gate; then

coupling the programming terminal of the tunneling capacitor to a semiconductor structure having electrical and thermal characteristics selected to match electrical and thermal characteristics of the first floating gate; and

generating a single-ended reference voltage in response to the programmed threshold voltage of the first NVM transistor while the programming terminal of the tunneling capacitor is coupled to the semiconductor structure.

2. The method of claim 1 , wherein the step of programming the threshold voltage of the first NVM transistor comprises applying a programming voltage across the programming terminal of the tunneling capacitor and the first floating gate.

3. The method of claim 1 , further comprising:

coupling a second NVM transistor in a current mirror configuration with the first NVM transistor during the step of programming the threshold voltage of the first NVM transistor; and

applying a reference voltage to the second NVM transistor during the step of programming the threshold voltage of the first NVM transistor.

4. The method of claim 3 , further comprising:

coupling the first NVM transistor and the second NVM transistor to a differential amplifier during the step of programming the threshold voltage of the first NVM transistor; and

terminating the step of programming the threshold voltage of the first NVM transistor when an output of the differential amplifier switches.

5. The method of claim 3 , further comprising initializing a threshold voltage of the second NVM transistor to a neutral state prior to programming the threshold voltage of the first NVM transistor.

6. The method of claim 5 , wherein the step of initializing the threshold voltage of the second NVM transistor comprises exposing the second NVM transistor to ultra-violet (UV) radiation.

7. The method of claim 1 , further comprising coupling a second NVM transistor in a current mirror configuration with the first NVM transistor during the step of generating the single-ended reference voltage.

8. The method of claim 7 , further comprising coupling the first NVM transistor and the second NVM transistor to inputs of a differential amplifier during the step of generating the single-ended reference voltage, wherein the differential amplifier provides the single-ended reference voltage.

9. The method of claim 7 , wherein a first current flows through the first NVM transistor during the step of generating the single-ended reference voltage, the method further comprising causing a current equal to the first current to flow through the semiconductor structure during the step of generating the single-ended reference voltage.

10. The method of claim 1 , further comprising erasing the first NVM transistor via the tunneling capacitor prior to programming the threshold voltage of the first NVM transistor.

11. The method of claim 1 , wherein the threshold voltage of the first NVM transistor is programmed by Fowler-Nordheim tunneling.

12. A voltage reference circuit for generating a reference voltage, comprising:

a first non-volatile memory (NVM) transistor having a first floating gate configured to store a programmed charge, wherein the reference voltage is generated in response to the programmed charge stored on the first floating gate;

a tunneling capacitor that shares the first floating gate with the first NVM transistor, wherein the tunneling capacitor has a programming terminal separate from the first floating gate;

a semiconductor structure having electrical and thermal characteristics selected to match electrical and thermal characteristics of the first NVM transistor;

a first switch configured to couple the programming terminal to the semiconductor structure during a normal operating mode in which the voltage reference circuit generates the reference voltage.

13. The voltage reference circuit of claim 12 , further comprising a second switch configured to couple the programming terminal to a programming voltage during a programming mode in which the programmed charge is stored on the first floating gate.

14. The voltage reference circuit of claim 12 , wherein the programming terminal comprises commonly coupled source/drain regions of a non-volatile memory transistor structure.

15. The voltage reference circuit of claim 12 , further comprising:

a second NVM transistor coupled in a common source configuration with the first NVM transistor; and

a differential amplifier having inputs coupled to the first and second NVM transistors, and an output configured to provide the reference voltage.

16. The voltage reference circuit of claim 15 , wherein the first NVM transistor is identical to the second NVM transistor and the semiconductor structure is a third NVM transistor identical to the first and second NVM transistors.

17. The voltage reference circuit of claim 12 , wherein the semiconductor structure comprises an NVM transistor structure comprising:

a drain region, wherein the first switch is coupled between the drain region and the programming terminal;

a control gate coupled to the drain region;

a second floating gate coupled to the control gate.

18. The voltage reference circuit of claim 17 , wherein the NVM transistor structure further comprises a source region commonly coupled to a source region of the first NVM transistor.

19. The voltage reference circuit of claim 12 , further comprising a bias transistor configured to introduce a current through the semiconductor structure, which is equal to a current through the first NVM transistor.