IP Library Granted Patent US 7,670,954
Granted Patent B2
US 7,670,954 · App. 11/943,984 · Granted Mar 2, 2010

Method of manufacturing semiconductor device

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Quick Facts
Patent No.
US 7,670,954
App. No.
11/943,984
Granted
Mar 2, 2010
Kind
B2
Abstract

Provided is a method of manufacturing a semiconductor device including at least two processes. Under an atmosphere comprising hydrogen and oxygen, a sacrificial oxide film is formed on a silicon substrate that is provided with at least one nitride region. Then, the sacrificial oxide film and the nitride region are removed from the silicon substrate.

Claims (34)

1. A method of manufacturing a semiconductor device comprising:

under an atmosphere comprising hydrogen and oxygen, forming a sacrificial oxide film on a silicon substrate provided with at least one nitride region;

removing the sacrificial oxide film and the nitride region from the silicon substrate.

2. The method of manufacturing a semiconductor device according to claim 1 , further comprising:

forming a trench on a silicon substrate by using a nitride film as a mask;

forming an isolation region made of oxide materials in the trench so that the silicon substrate is provided with the nitride region.

3. The method of manufacturing a semiconductor device according to claim 1 , wherein the forming a sacrificial oxide film is carried out at 800° C. or higher.

4. The method of manufacturing a semiconductor device according to claim 1 , wherein the forming a sacrificial oxide film is carried out at 1000° C.

5. The method of manufacturing a semiconductor device according to claim 1 , wherein the forming a sacrificial oxide film comprises forming the sacrificial oxide film on at least one device formation region of the silicon substrate.

6. A method of manufacturing a semiconductor device comprising:

forming a trench on a silicon substrate by using a nitride film as a mask;

forming an isolation region made of oxide materials in the trench so that the silicon substrate is provided with at least one nitride region;

under an atmosphere comprising hydrogen and oxygen, forming a sacrificial oxide film on the silicon substrate provided with the at least one nitride region; and

removing the sacrificial oxide film and the nitride region from the silicon substrate;

wherein the forming an isolation region comprises:

forming a first oxide film on the trench by wet oxidation to obtain an oxide trench; and

filling the oxide trench with a second oxide film to form the isolation region.

7. The method of manufacturing a semiconductor device according to claim 6 , wherein the forming a sacrificial oxide layer is carried out so that the sacrificial oxide film has a thickness substantially equal to three-fifth of another thickness of the first oxide film.

8. The method of manufacturing a semiconductor device according to claim 6 , wherein the forming a sacrificial oxide film comprising adjusting a thickness of the sacrificial oxide film so that the thickness of the sacrificial oxide film is proportional to the thickness of the first oxide film.

9. A method of manufacturing a semiconductor device, comprising:

forming a pad silicon oxide film on a silicon substrate;

forming a silicon nitride film on the pad silicon oxide film;

patterning a part of the pad silicon oxide film and the silicon nitride film to expose a first surface region of the silicon substrate;

selectively etching the silicon substrate using the silicon nitride film as a mask to form a trench;

forming a liner silicon oxide film on a surface of the trench;

forming a filling insulation film, with which the trench is filled, on the liner silicon oxide film;

removing the silicon nitride film and the pad silicon oxide film to expose a second surface region of the silicon substrate;

covering the second surface region of the silicon substrate with a sacrificial oxide film by heat oxidation under an atmosphere comprising hydrogen and oxygen;

removing the sacrificial oxide film to a newly exposed surface which corresponds to the second surface region of the silicon substrate; and

forming a gate insulation film on the newly-exposed surface.

10. The method of manufacturing a semiconductor device according to claim 9 , wherein the atmosphere contains O atomic radicals and OH − molecular radicals.

11. The method of manufacturing a semiconductor device according to claim 9 , wherein the thickness of the sacrificial oxide film is three-fifths of the thickness of the liner oxide film.

12. The method of manufacturing a semiconductor device according to claim 9 , wherein the thickness of the sacrificial oxide film is adjusted so that it is proportional to the thickness of the liner oxide film.

13. The method of manufacturing a semiconductor device according to claim 10 , wherein the temperature of the atmosphere is 800° C. or higher.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2014
From: ELPIDA MEMORY, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032645/0422 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2007
From: OHASHI, TAKUO
To: ELPIDA MEMORY, INC.
Reel/Frame 020217/0562 →