Lateral MOS transistor and method for manufacturing thereof
View Patent ↗A lateral MOS transistor that can include a first device isolating layer formed in a semiconductor substrate; a second device isolating layer formed in the semiconductor substrate, the second device isolation layer having a different width than the first device isolation layer and also having an etched groove provided therein; a gate insulating layer formed in the etched groove; a gate electrode formed over the gate insulating layer; and a source/drain region horizontally arranged in the semiconductor substrate adjacent to the gate electrode.
1. An apparatus comprising:
a first device isolating layer formed in a semiconductor substrate;
a second device isolating layer formed in the semiconductor substrate, the second device isolation layer having a different width than the first device isolation layer and also having an etched groove provided therein;
a gate insulating layer formed in the etched groove;
a gate electrode formed over the gate insulating layer; and
a source/drain region horizontally arranged in the semiconductor substrate adjacent the gate electrode,
wherein the gate electrode and the source/drain region have uppermost surfaces in a substantially same plane as a uppermost surface of the semiconductor substrate.
2. The apparatus of claim 1 , wherein the first device isolation layer and the second device isolating layer have an STI structure.
3. The apparatus of claim 1 , wherein the width of the second isolating layer is larger than the combined widths of the first device isolating layer and the gate electrode.
4. The apparatus of claim 1 , further comprising:
an interlayer dielectric layer formed over the semiconductor substrate including the source/drain region and the gate electrode; and
at least one contact electrode provided in the interlayer dielectric layer and electrically connected to at least one of the gate electrode and the source/drain region.
5. The apparatus of claim 4 , wherein the interlayer dielectric layer is composed of at least one of PSG, BSG, BPSG, and USG.
6. A method comprising:
forming a first device isolating layer and a second device isolating layer having different widths in a semiconductor substrate;
forming a groove in the second device isolating layer;
forming a gate insulating layer in the etched groove;
forming a gate electrode over the gate insulating layer to gap-fill the groove; and then
forming at least one source/drain region horizontally arranged in the semiconductor substrate adjacent to the gate electrode,
wherein the gate electrode and the at least one source/drain region have uppermost surfaces in a substantially same plane as a uppermost surface of the semiconductor substrate.
7. The method of claim 6 , wherein the first device isolating layer and the second device isolating layer are formed having a STI structure.
8. The method of claim 6 , wherein the width of the second isolating layer is larger than the combined widths of the first device isolating layer and the gate electrode.
9. The method of claim 6 , wherein the source/drain region is formed having an LDD structure.
10. The method of claim 6 , wherein after forming the at least one source/drain region, further comprising:
forming a silicide film over at least one of the gate electrode and the source/drain region.
11. The method of claim 10 , further comprising:
forming an interlayer dielectric layer over the semiconductor substrate including the silicide film formed over at least one of the gate electrode and the source/drain region;
forming at least one contact hole in the interlayer dielectric layer; and
forming a contact electrode in the at least one contact hole vertically and electrically connected to at least one of the gate electrode and the source/drain region.
12. A method comprising:
forming a first device isolating layer and a second device isolating layer in a semiconductor substrate;
forming a groove in the second device isolating layer;
forming a gate insulating layer in the groove;
forming a gate electrode connecting wiring over the gate insulating layer to gap-fill the groove;
forming a gate electrode electrically connected to the gate electrode connecting wiring on a portion of the uppermost surface of the second device isolating layer; and then
forming at least one source/drain region horizontally arranged in the semiconductor substrate adjacent to the gate electrode connecting wiring,
wherein the gate electrode and the at least one source/drain region are spaced apart from each other through the gate electrode connecting wiring therebetween.
13. The method of claim 12 , wherein after forming the at least one source/drain region, further comprising:
forming a silicide film over at least one of the gate electrode and the source/drain region.
14. The method of claim 13 , further comprising:
forming an interlayer dielectric layer over the semiconductor substrate including the silicide film formed over at least one of the gate electrode and the source/drain region;
forming at least one contact hole in the interlayer dielectric layer; and
forming a contact electrode in the at least one contact hole vertically and electrically connected to at least one of the gate electrode and the source/drain region.
15. The method of claim 14 , wherein the silicide film comprises titanium silicide.
16. The method of claim 15 , wherein the interlayer dielectric layer is composed of at least one of PSG, BSG, BPSG, and USG.
17. The method according to claim 12 , wherein the first device isolating layer and the second device isolating layer are formed having a STI structure.
18. The method according to claim 12 , wherein the width of the second isolating layer is larger than the combined widths of the first device isolating layer and the gate electrode.
19. The method according to claim 15 , wherein the source/drain region is formed having a LDD structure.
20. The method of claim 14 , wherein the groove is formed by etching a portion of any one edge surface of the second device isolating layer to a predetermined depth.