IP Library Granted Patent US 7,696,560
Granted Patent B2
US 7,696,560 · App. 11/945,206 · Granted Apr 13, 2010

Flash memory device

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Quick Facts
Patent No.
US 7,696,560
App. No.
11/945,206
Granted
Apr 13, 2010
Kind
B2
Abstract

A flash memory device includes control gates that are formed to completely surround the top and sides of floating gates. The control gates are located between the floating gates that are adjacent in the word line direction as well as the floating gates that are adjacent in the bit line direction. The present flash memory device reduces a shift in a threshold voltage resulting from interference among floating gates and increases an overlapping area of the floating gate and the control gates. Thus, there is an effect in that the coupling ratio can be increased.

Claims (11)

1. A flash memory device, comprising:

a semiconductor substrate;

a tunnel dielectric film formed over the semiconductor substrate;

floating gates formed over the tunnel dielectric film and separated in an island shape on a cell basis;

an interlayer dielectric film formed over the entire surface including the floating gates; and

control gates formed over the interlayer dielectric film and arranged in a first direction while surrounding the top surface and sidewalls of the floating gates,

wherein an area where each control gate surrounds one sidewall of the corresponding floating gate is equal to an area where each control gate surrounds another sidewall of the corresponding floating gate in a word line direction.

2. The flash memory device as claimed in claim 1 , wherein a width of the control gates in a second direction perpendicular to the first direction corresponds to the sum of a width of the floating gates in the second direction, twice a thickness of the interlayer dielectric film, and overlay margin.

3. The flash memory device as claimed in claim 2 , wherein the overlay margin is the sum of a minimum thickness of the control gates that are formed at both sides of the floating gates in the second direction and misalignment margin.

4. The flash memory device as claimed in claim 3 , wherein the minimum thickness of the control gates that are formed at both sides of the floating gates in the second direction is 10 nm.

5. The flash memory device as claimed in claim 2 , wherein the floating gates are a square, circular, elliptical or polygonal shape.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE IS HYNIX SEMICONDUCTOR INC. NOT HYNIX-SEMICONDUCTOR INC. THERE IS NO HYPHEN IN THE NAME. PREVIOUSLY RECORDED ON REEL 67328 FRAME 814. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded May 14, 2024
From: HYNIX SEMICONDUCTOR INC.
To: SK HYNIX INC.
Reel/Frame 067412/0482 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2024
From: SK HYNIX INC.
To: MIMIRIP LLC
Reel/Frame 067369/0832 →
CHANGE OF NAME Recorded May 6, 2024
From: HYNIX-SEMICONDUCTOR INC.
To: SK HYNIX INC.
Reel/Frame 067328/0814 →