Semiconductor integrated circuit with input buffer having high voltage protection
View Patent ↗A high voltage reception terminal is formed in a semiconductor integrated circuit without increasing the number of manufacturing processes and the manufacturing cost. A transfer gate configured from a NMOS, which is the high withstand voltage transistor, and a pull-up resistor are formed. An input terminal of the transfer gate is connected to the high voltage reception terminal and an output terminal of the transfer gate is connected to a CMOS inverter through an input resistor. One end of the pull-up resistor is connected to the output terminal of the transfer gate and the other end of the pull-up resistor receives source voltage VDD (5V). The transfer gate lowers the inputted high voltage VX (VX>VDD) to VDD-Vt1′. The pull-up resistor biases the voltage at the output terminal of the transfer gate to VDD and boosts the voltage at the output terminal that has been lowered by the transfer gate to about VDD.
1. A semiconductor integrated circuit comprising:
a high voltage reception terminal receiving a negative high voltage lower than a ground voltage;
a transfer gate comprising a first MOS transistor of an P channel type withstanding the negative high voltage, the first MOS transistor comprising an input terminal electrically connected to the high voltage reception terminal and a gate receiving the ground voltage;
an input buffer comprising a second MOS transistor comprising a gate electrically connected to an output terminal of the first MOS transistor; and
a pull-down device electrically connected to the output terminal of the first MOS transistor and biasing the output terminal to the ground voltage,
wherein the high voltage reception terminal and the transfer gate are connected directly so that no transistor intersects a current path between the high voltage reception terminal and the transfer gate.
2. The semiconductor integrated circuit of claim 1 , further comprising an output transistor comprising a third MOS transistor of a P channel type withstanding the negative high voltage and electrically connected to the high voltage reception terminal.
3. A semiconductor integrated circuit comprising:
a high voltage reception terminal receiving a positive high voltage higher than a power source voltage;
a transfer gate comprising a first MOS transistor of an N channel type withstanding the positive high voltage, the first MOS transistor comprising an input terminal electrically connected to the high voltage reception terminal and a gate receiving the power source voltage;
an input buffer comprising a second MOS transistor comprising a gate electrically connected to an output terminal of the first MOS transistor; and
a pull-up device electrically connected to the output terminal of the first MOS transistor and biasing the output terminal to the power source voltage,
wherein a resistance of the pull-up device is sufficiently higher than a resistance of the transfer gate that a voltage at the output terminal of the first MOS transistor becomes substantially a ground voltage when the ground voltage is applied to the high voltage reception terminal.
4. A semiconductor integrated circuit comprising:
a high voltage reception terminal receiving a negative high voltage lower than a ground voltage;
a transfer gate comprising a first MOS transistor of an P channel type withstanding the negative high voltage, the first MOS transistor comprising an input terminal electrically connected to the high voltage reception terminal and a gate receiving the ground voltage;
an input buffer comprising a second MOS transistor comprising a gate electrically connected to an output terminal of the first MOS transistor; and
a pull-down device electrically connected to the output terminal of the first MOS transistor and biasing the output terminal to the ground voltage,
wherein a resistance of the pull-down device is sufficiently higher than a resistance of the transfer gate that a voltage at the output terminal of the first MOS transistor becomes substantially a power source voltage when the power source voltage is applied to the high voltage reception terminal.