Granted Patent B2

US 8,126,018 · App. 11/946,635 · Granted Feb 28, 2012

Abstract

Claims (9)

1. A decoding circuit operable to decode coded video data including non-reference frame data and reference frame data, comprising:

a data storage memory configured to successively store the coded video data of each frame; and

a start address storage unit configured to memorize a start address of non-reference frame data stored in the data storage memory,

wherein the decoding circuit performs a decoding operation in response to a decoding start command, so that reading of the data initiates from the start address of already stored non-reference frame data;

wherein the coded video data includes 12-segment frame data and one-segment frame data;

wherein, when the decoding circuit is performing a decoding operation for the 12-segment frame data, the data storage memory stores the one-segment frame data and the start address storage unit memorizes a start address of one-segment non-reference frame; and

wherein the decoding circuit starts a decoding operation for the one-segment data in response to a one-segment data decoding command so that reading of the data initiates from the start address of the already stored non-reference frame data.

2. The decoding circuit according to claim 1 , wherein the decoding circuit detects display time information relating to the read non-reference frame data in response to the decoding start command, and adjusts a decoding speed to decease a difference between the display time and the present time.

3. The decoding circuit according to claim 1 , wherein the reading of the data initiated from the start address by the decoding circuit is delayed from the present time such that the data displayed using the decoding circuit is initially delayed from the present time.

Assignments (8)