Semiconductor memory device with dummy bit lines for charge and discharge timing
View Patent ↗The invention provides a semiconductor memory device which realizes high speed reading by automatically adjusting and optimizing charge and discharge timings even when a change in an operation environment such as a variation in an operation voltage, an operation temperature, a process parameter and so on occurs. First and second dummy bit lines are provided for a bit line, each having a wiring load twice the wiring load of the bit line. A first sense circuit sensing the voltage of the first dummy bit line is provided to control a charging time according to a first sense signal. A second sense circuit sensing the voltage of the second dummy bit line is further provided to control a discharging time according to a second sense signal. A sense amplifier sensing the voltage of the bit line is activated in response to the second sense signal.
1. A semiconductor memory device comprising:
a memory cell transistor;
a bit line connected to the memory cell transistor;
a sense amplifier activated by a sense enable signal and sensing a voltage of the bit line;
a first dummy memory cell transistor;
a first dummy bit line connected to the first dummy memory cell transistor and having a wiring load larger than a wiring load of the bit line;
a first sense circuit sensing a voltage of the first dummy bit line and outputting a first sense signal;
a precharge circuit charging the bit line and the first dummy bit line;
a second dummy memory cell transistor;
a second dummy bit line connected to the second dummy memory cell transistor and having a wiring load larger than the wiring load of the bit line;
a discharge circuit discharging the bit line and the second dummy bit line;
a second sense circuit sensing a voltage of the second dummy bit line and outputting a second sense signal; and
a read control circuit starting a charging operation of the precharge circuit in response to a read enable signal, ending the charging operation of the precharge circuit and starting a discharging operation of the discharge circuit in response to the first sense signal of the first sense circuit, and outputting the sense enable signal in response to the second sense signal of the second sense circuit,
wherein the first dummy memory cell transistor is connected to only one dummy bit line, and the second dummy memory cell transistor is connected to only one dummy bit line.
2. The semiconductor memory device of claim 1 , wherein each of the first and second dummy bit lines comprises a plurality of bit lines connected in serial.
3. The semiconductor memory device of claim 1 , wherein each of the first and second sense circuits comprises an inverter.
4. The semiconductor memory device of claim 2 , wherein each of the first and second sense circuits comprises an inverter.
5. The semiconductor memory device of claim 1 , wherein the read control circuit adjusts a voltage of a word line connected to the memory cell transistor when data is read out from the memory cell transistor, based on the second sense signal.
6. The semiconductor memory device of claim 1 , wherein each of the first and second dummy bit lines comprises two bit lines connected in serial, and a column of a memory array of the memory device corresponding to each of the four bit lines includes a dummy memory cell transistor.
7. The semiconductor memory device of claim 1 , wherein all dummy memory cell transistors connected to the second dummy bit line store the same bit data.