Data I/O control signal generating circuit in a semiconductor memory apparatus
View Patent ↗A circuit for generating a data I/O control signal used in a semiconductor memory apparatus comprises a delay block for generating a delay signal having a relatively short delay value and a delay signal having a relatively long delay values, and a selection block for selecting any one of the delay signals according to an operational mode. The selection block selects an output signal of the first delay unit in a high-speed operation mode and selects an output signal of the second delay unit in a low-speed operation mode.
1. A circuit for generating a data I/O control signal used in a semiconductor memory apparatus, comprising:
a delay block for generating a delay signal having a relatively short delay value and a delay signal having a relatively long delay value; and
a selection block for selecting any one of the delay signals according to a speed type of an operation mode,
wherein the selection block is configured to select the delay signal having a relatively short delay value in a high-speed operation mode, and is configured to select the delay signal having a relatively long delay value in a low-speed operation mode,
wherein the high-speed operation mode signal is a signal which is enabled in a high level when a CAS latency signal is more than a predetermined value, and
wherein the low-speed operation mode signal is a signal which is enabled in a high level when the CAS latency signal is less than the predetermined value.
2. The circuit of claim 1 , wherein the delay block includes:
a first delay unit for generating the delay signal having a relatively short delay value; and
a second delay unit for generating the delay signal having a relatively long delay value.
3. The circuit of claim 1 , wherein the selection block includes:
a first pass gate for transferring the output signal of the first delay unit according to a high-speed operation mode signal; and
a second pass gate for transferring the output signal of the second delay unit according to a low-speed operation mode signal.
4. The circuit of claim 1 , wherein the delay block receives the clock pulse to generate a clock pulse delayed for a relatively short time and a clock pulse delayed for a relatively long time, and
wherein the selection block further includes a signal combination unit for generating a column selection signal by logically combining the clock pulse with any one of a clock pulse delayed for the relatively short time and the clock pulse delayed for the relatively long time.
5. The circuit of claim 1 , wherein the delay block receives the column selection signal to generate a column selection signal delayed for a relatively short time and a column selection signal delayed for a relatively long time, and
wherein the selection block outputs any one of the column selection signal delayed for a relatively short time and the column selection signal delayed for a relatively long time as an input/output strobe signal.
6. A circuit for generating a data I/O control signal used in a semiconductor memory apparatus, comprising:
a delay block including a first delay unit for delaying a clock pulse as much as a first delay value and a second delay unit for delaying the clock pulse as much as a second delay value which is larger than the first delay value;
a signal selecting unit for selecting a signal of the first delay unit in the high-speed operation mode and selecting a signal of the second delay unit in the low-speed operation mode; and
a signal combination unit for generating a column selection signal by logically combining the output signal of the signal selecting unit with the clock pulse,
wherein the high-speed operation mode signal is a signal which is enabled in a high level when a CAS latency signal is more than a predetermined value and wherein the low-speed operation mode signal is a signal which is enabled in a high level when the CAS latency signal is less than the predetermined value.
7. The circuit of claim 6 , wherein the signal selecting unit includes:
a first pass gate for transferring the output signal of the first delay unit according to a high-speed operation mode signal; and
a second pass gate for transferring the output signal of the second delay unit according to a low-speed operation mode signal.
8. The circuit of claim 6 , wherein the signal combination unit OR operates the output signal of the signal selecting unit and the clock pulse.
9. A circuit for generating a data I/O control signal used in a semiconductor memory apparatus, comprising:
a first delay block including a first delay unit for delaying a clock pulse as much as a first delay value and a second delay unit for delaying the clock pulse as much as a second delay value which is larger than the first delay value;
a selection block for selecting a signal of the first delay unit in the high-speed operation mode and selecting a signal of the second delay unit in the low-speed operation mode;
a second delay block including a third delay unit for delaying a clock pulse as much as a third delay value and a fourth delay unit for delaying the clock pulse as much as a fourth delay value which is larger than the third delay value; and
a transfer block for outputting a signal of the third delay unit as an input/output strobe signal in the high-speed operation mode and outputting a signal of the fourth delay unit as the input/output strobe signal in the low-speed operation mode.
10. The circuit of claim 9 , wherein the selection block includes:
a first pass gate for transferring the output signal of the first delay unit according to a high-speed operation mode signal; and
a second pass gate for transferring the output signal of the second delay unit according to a low-speed operation mode signal.
11. The circuit of claim 10 , wherein the selection block further includes a signal combination unit for generating a column selection signal by logically combining any one of the output signal of the first pass gate or the output signal of the second pass gate selected by the selection block with the clock pulse.
12. The circuit of claim 9 , wherein the transfer block includes:
a third pass gate for transferring the output signal of the third delay unit according to a high-speed operation mode signal; and
a fourth pass gate for transferring the output signal of the fourth delay unit according to a low-speed operation mode signal.
13. The circuit of claim 9 , wherein the high-speed operation mode signal is a signal which is enabled in a high level when a CAS latency signal is more than a predetermined value and wherein the low-speed operation mode signal is a signal which is enabled in a high level when the CAS latency signal is less than the predetermined value.