High speed serial trace protocol for device debug
Tracing of test information from a hardware device for debugging is formatted for transmission via a high-speed serial protocol. Data from various components in the hardware device is transmitted to an external test board using high speed serial ports. The number of serial ports needed for data transfer is significantly less than a complimentary parallel port configuration. Additional functional blocks on the chip process the data for high speed serial output. The functional blocks format information into subchannels, arbitrate data, append protocol, perform data integrity checks, and serialize the data. The additional blocks built on the chip to support the serial ports consume less chip space than the space consumed by the number of parallel ports required to provide equivalent data transfer rates. The process operates in near real time and may use time stamping to correlate and reconstruct data from different information sources. An input port receives data from the external test component to modify registers or memory, set break points, modify hardware status, communicate with processors, or modify other operating conditions to debug the hardware device.
1. An operational component in a hardware device comprising:
a formatter that receives a trace data output from a plurality of functional blocks adapted to output trace data for use in a debugging process and transforms the trace data from each of the functional blocks into data packets of a common format and a uniform data rate;
an arbitrator that manages an output of multiple data streams from the formatter based upon one or more programmable scheduling schemes to determine a selection of data packets from each of the multiple data streams for output as a serial data stream; and
a serial data port that outputs the serial data stream from the operational component.
2. The operational component of claim 1 , wherein
the formatter comprises a plurality of formatters corresponding respectively to each of the functional blocks; and wherein the operational component further comprises
a plurality of buffers corresponding respectively to each of the plurality of formatters that receive the data packets from the respective formatters; and wherein
the arbitrator further monitors data fill levels in each of the buffers and changes between the scheduling schemes to prevent overflow in any of the buffers; and
each of the buffers stores packets of trace data corresponding to a respective functional block until the arbitrator directs output of the data packets from a particular one of the buffers.
3. The operational component of claim 2 , wherein the formatters insert a time stamp into the trace data for correlation of substantially simultaneous events occurring at two or more of the functional blocks.
4. The operational component of claim 1 further comprising
a transmission protocol engine that receives the serial data stream output from the arbitrator and adds synchronization values to the serial data stream for use by a test component receiving the serial data stream to implement a blind lock with the operational component.
5. The operational component of claim 4 , wherein the transmission protocol engine further applies a data integrity scheme to the serial data stream to mitigate errors due to transmission of the serial data stream when reconstituted after receipt at a test component.
6. The operational component of claim 1 , wherein the serial data port comprises a plurality of subchannels and the serial data port distributes the serial data stream among the plurality of subchannels to increase throughput.
7. The operational component of claim 1 , wherein the serial data port comprises an input port to receive return data from an external test component.
8. The operational component of claim 1 , wherein
the operational component is an integrated circuit chip with a number of output pins corresponding to the serial data port; and
the number of output pins is less than a second number of output pins that would be required for a comparable integrated circuit chip using one or more parallel ports to output an equivalent quantity of the trace data at an equivalent data rate.
9. A method for performing a serial trace debug of a hardware device, the method comprising:
outputting trace data from a plurality of functional blocks in an operational component of the hardware device;
transforming the trace data from each of the functional blocks into multiple data packets of a common format and a uniform data rate;
managing the data streams based upon one or more programmable scheduling schemes that determine a selection of the trace data for output;
multiplexing the selected trace data from the multiple data streams into a serial data stream; and
transmitting the serial data stream from the operational component to a test component.
10. The method of claim 8 further comprising
buffering the multiple data streams corresponding to each of the functional blocks in a respective plurality of first-in, first-out storage buffers; and
monitoring data fill levels in each of the buffers and implementing changes between the scheduling schemes to prevent overflow in any of the buffers before the multiplexing operation.
11. The method of claim 8 further comprising inserting a time stamp into the trace data for correlation of simultaneous events occurring at two or more of the functional blocks.
12. The method of claim 8 further comprising applying a data integrity scheme to the serial data stream to mitigate errors due to transmission of the serial data stream when reconstituted after receipt at a test component.
13. The method of claim 8 further comprising inserting synchronization values into the serial data stream for use by a test component receiving the serial data stream to implement a blind phase lock with the operational component.
14. The method of claim 8 further comprising distributing the serial data stream among a plurality of serial output port subchannels to increase throughput of the serial data stream.
15. A hard disk drive comprising
a plurality of functional blocks adapted to output trace data for use in a debugging process;
a plurality of formatters, corresponding respectively to each of the functional blocks, that receive the trace data output from the functional blocks and transform the trace data from each of the functional blocks into data packets of a common format and output the data packets at a uniform data rate in multiple data streams each corresponding to a respective functional block;
a plurality of buffers, corresponding respectively to each of the plurality of formatters, that store the data packets of respective ones of the multiple data streams;
a multiplexer that receives output from the buffers of the multiple data streams corresponding to the data packets output from each of the functional blocks and combines the multiple data streams into a serial data stream;
an arbitrator that manages the output of the multiple data streams from the buffers for input into the multiplexer based upon one or more programmable scheduling schemes that determine the selection of a particular one of the multiple data streams for input;
a transmission protocol engine that receives the serial data stream output from the multiplexer and adds synchronization values to the serial data stream for use by a test component receiving the serial data stream to implement a blind phase lock with the operational component; and
a serial data port that outputs the serial data stream from the operational component.
16. The hard disk drive of claim 15 , wherein the arbitrator further monitors data fill levels in each of the buffers and changes between the scheduling schemes to prevent overflow in any of the buffers.
17. The hard disk drive of claim 15 , wherein the formatters are synchronized and insert a time stamp into the trace data for correlation of simultaneous events occurring at two or more of the functional blocks.
18. The hard disk drive of claim 15 , wherein the transmission protocol engine further applies a data integrity scheme to the serial data stream to mitigate errors due to transmission of the serial data stream when reconstituted after receipt at a test component.
19. The hard disk drive of claim 15 , wherein the serial data port comprises a plurality of subchannels and the serial data port distributes the serial data stream among the plurality of subchannels to increase throughput.
20. The hard disk drive of claim 15 , wherein the serial data port comprises an input port to receive return data from an external test component.
21. The hard disk drive of claim 15 , wherein
the functional blocks are components of an integrated circuit chip with a number of output pins corresponding to the serial data port; and
the number of output pins is less than a second number of output pins that would be required for a comparable integrated circuit chip using one or more parallel ports to output an equivalent quantity of the trace data at an equivalent data rate.