Flash memory cell transistor with threshold adjust implant and source-drain implant formed using a single mask
View Patent ↗A method for forming an NMOS transistor for use in a flash memory cell on a P-type semiconductor structure includes forming a photoresist layer over the semiconductor structure and patterning the photoresist layer using a source/drain mask for the NMOS transistor; forming a first N-type region and a second N-type region by a first implantation process using the patterned photoresist as an implant mask where the first implantation process uses a high implant dose at a low implant energy and the first and second N-type regions form the source and drain regions of the NMOS transistor; forming a channel doped region by a second implantation process using the patterned photoresist as an implant mask where the second implantation process uses a low implant dose at a high implant energy and the channel doped region is formed for adjusting a threshold voltage of the NMOS transistor.
1. A method for forming an NMOS transistor for use in a flash memory cell on a P-type semiconductor structure, the NMOS transistor having a polysilicon gate being a floating gate and being connected to an electrode of a coupling capacitor, the other electrode of the coupling capacitor being the control terminal of the flash memory cell, the method comprising:
forming a P-well in the P-type semiconductor structure;
defining active areas on the P-type semiconductor structure including at least a first active area in which a channel region, a source region and a drain region are to be formed;
forming a gate dielectric layer over the P-type semiconductor structure;
forming a polysilicon layer over the gate dielectric layer and patterning the polysilicon layer to form the polysilicon gate of the NMOS transistor;
forming a photoresist layer over the semiconductor structure and patterning the photoresist layer using a source/drain mask for the NMOS transistor, the patterned photoresist layer exposing the first active area;
forming a first N-type region and a second N-type region by a first implantation process using the patterned photoresist as an implant mask, the first implantation process using a high implant dose at a low implant energy, the first and second N-type regions being self-aligned to the polysilicon gate and forming the source and drain regions of the NMOS transistor;
forming a channel doped region by a second implantation process using the patterned photoresist as an implant mask, the second implantation process using a low implant dose at a high implant energy, the channel doped region being formed under the polysilicon gate for adjusting a threshold voltage of the NMOS transistor; and
removing the patterned photoresist.
2. The method of claim 1 , wherein forming a first N-type region and a second N-type region by a first implantation process comprises performing the first implantation process using an implant dose of at least 10 15 and an implant energy of less than 100 KeV.
3. The method of claim 1 , wherein forming a channel doped region by a second implantation process comprises performing the second implantation process using an implant dose of about 10 12 and an implant energy of greater than 100 KeV.
4. The method of claim 1 , wherein the P-type semiconductor structure comprises a P-type semiconductor substrate and a P-type epitaxial layer form on the semiconductor substrate.
5. The method of claim 1 , wherein the first implantation process is performed before the second implantation process.
6. The method of claim 1 , wherein the first implantation process is performed after the second implantation process.