Granted Patent B2

US 7,443,148 · App. 11/955,157 · Granted Oct 28, 2008

Abstract

Claims (26)

1. A buck switching regulator formed on an integrated circuit and receiving an input voltage, the buck switching regulator controlling a high-side switch and a low-side switch using a feedback control loop to drive a switch output node for generating a switching output voltage, the switch output node being coupled to an LC filter circuit external to the integrated circuit to generate a regulated output voltage having a substantially constant magnitude on an output node, the regulated output voltage being fed back to the buck switching regulator to a voltage divider for generating a feedback voltage on a feedback voltage node, the buck switching regulator comprising:

an on-time control circuit for generating a first signal for controlling the high-side switch under a minimum on-time and variable off-time feedback control loop, the first signal turning off the high-side switch at the expiration of a first on-time duration or at the expiration of a maximum on-time, the first on-time duration being at least a minimum on-time and being expanded to the maximum on-time when the feedback voltage remains less than a reference voltage, and the maximum on-time comprising a first maximum on-time and a second, extended maximum on-time greater than the first maximum on-time, wherein the second, extended maximum on-time is applied when a minimum off-time was used for the high-side switch during the previous switching cycle.

2. The buck switching regulator of claim 1 , wherein the first maximum on-time is set by a first capacitor and the second maximum on-time is set by the addition of a second capacitor in parallel with the first capacitor.

3. The buck switching regulator of claim 1 , wherein the first maximum on-time is set by a first capacitance value and the second maximum on-time is set by the addition of a second capacitance value to the first capacitance value.

4. The buck switching regulator of claim 1 , wherein the second, extended maximum on-time is applied when a minimum off-time was used for the high-side switch during the previous switching cycle and when an output current of the switching regulator is not being current limited.

5. The buck switching regulator of claim 1 , wherein the on-time control circuit comprises a maximum on-time control circuit for generating a second signal at the expiration of the first maximum on-time or the second maximum on-time, the maximum on-time control circuit comprising:

a first timer circuit comprising a first capacitor connected in parallel with a first transistor between a first node and a ground node, and a current source coupled to charge the first capacitor, the first transistor being controlled by the first signal; and

a comparator comparing a first voltage at the first node to a second DC reference voltage, the comparator generating an output voltage being the second signal, the second signal being asserted when the first voltage is equal to or greater than the second DC reference voltage,

wherein when the high-side switch is turned off, the first signal is asserted to turn on the first transistor, thereby discharging the first capacitor; and when the high-side switch is turned on, the first signal is deasserted to turn off the first transistor to allow the first capacitor to be charged by the current source, the first voltage thereby increasing, and wherein the first maximum on-time comprises the time duration for the first voltage to reach the second DC reference voltage.

6. The buck switching regulator of claim 5 , wherein the maximum on-time control circuit further comprises:

a second timer circuit comprising a second transistor connected in series with a second capacitor between the first node and the ground node, the second transistor being controlled by a third signal, the third signal being asserted to turn on the second transistor when a minimum off-time is used for the high-side switch during a previous switching cycle,

wherein the second transistor is turned on to connect the second capacitor in parallel with the first capacitor, and wherein the second maximum on-time comprises the time duration for the first voltage to reach the second DC reference voltage by charging of the first and second capacitors.

7. The buck switching regulator of claim 6 , wherein the second timer circuit further comprises:

a one-shot circuit for generating a minimum-off-time pulse indicative of the minimum off-time being reached;

a first logic gate for receiving the minimum-off-time pulse and a fourth signal and generating an output signal being asserted when the fourth signal is asserted during the minimum-off-time pulse; and

a set-reset flip-flop having a set input terminal receiving the output signal of the first logic signal, a reset input terminal receiving the first signal and an output terminal generating the third signal.

8. The buck switching regulator of claim 7 , wherein the first logic gate further receives a fifth signal indicating that an output current of the switching regulator is not being current limited, the first logic gate asserting the output signal when the fourth signal is asserted during the minimum-off-time pulse and the fifth signal is asserted.

9. A method in buck switching regulator receiving an input voltage and controlling a high-side switch and a low-side switch using a feedback control loop to drive a switch output node for generating a switching output voltage, the switch output node being coupled to an LC filter circuit to generate a regulated output voltage having a substantially constant magnitude on an output node, the regulated output voltage being fed back to the buck switching regulator to a voltage divider for generating a feedback voltage on a feedback voltage node, the method comprising:

providing a first on-time duration for the high-side switch being at least a minimum on-time and being expanded to a maximum on-time when the feedback voltage remains less than a reference voltage;

providing a first maximum on-time or a second, extended maximum on-time greater than the first maximum on-time as the maximum on-time;

applying the first maximum on-time when a minimum off-time was not used for the high-side switch during the previous switching cycle;

applying the second, extended maximum on-time when a minimum off-time was used for the high-side switch during the previous switching cycle; and

generating a first signal for turning off the high-side switch under a minimum on-time and variable off-time feedback control loop, the first signal turning off the high-side switch at the expiration of the first on-time duration or at the expiration of the first or second maximum on-times.

10. The method of claim 9 , wherein providing a first maximum on-time comprises providing the first maximum on-time by charging of a first capacitor and providing a second, extended maximum on-time comprises providing the second, extended maximum on-time by charging of the first capacitor and a second capacitor connected in parallel with the first capacitor.

11. The method of claim 9 , wherein providing a first maximum on-time comprises providing the first maximum on-time by charging of a first capacitance value and providing a second, extended maximum on-time comprises providing the second, extended maximum on-time by charging of a second capacitance value being the sum of the first capacitance value and a third capacitance value.

12. The method of claim 9 , wherein providing a second, extended maximum on-time greater than the first maximum on-time comprises providing the second, extended maximum on-time when a minimum off-time is used for the high-side switch during a previous switching cycle and when an output current of the switching regulator is not being current limited.

Assignments (10)