Signal processing circuit for accessing a memory based on adjustable memory control clock
View Patent ↗A delay time of a reference clock CLK is changed to generate a memory control clock CLKd, a data value output from a write data generating section is written in a memory based on the memory control clock CLKd, while successively changing the delay time of the memory control clock CLKd with respect to the reference clock CLK, the data value written in the memory is read, and the delay time suitable for access to the memory is selected from the delay time of the memory control clock CLKd with respect to the reference clock CLK based on a comparison result of the data values.
1. A signal processing circuit which processes a signal based on a reference clock,
the signal processing circuit being connected to a memory in which data is written and read based on a memory control clock,
the signal processing circuit comprising:
a timing adjustment section which changes a delay time of the memory control clock generated by delaying the reference clock, to output the memory control clock to the memory;
a write data generating section which outputs, to the memory, a predetermined data value to be written in the memory; and
a read comparison section which reads a data value stored in the memory to compare the data value with the predetermined data value,
the signal processing circuit being configured to execute writing processing to write the data value output from the write data generating section in the memory based on the memory control clock, while the timing adjustment section successively changes the delay time of the memory control clock with respect to the reference clock, and reading processing to read the data value written in the memory by the writing processing, and being configured to select a delay time suitable for access to the memory from the delay time of the memory control clock with respect to the reference clock, based on a result of the comparison between the data value read by the reading processing and the predetermined data value in the read comparison section.
2. The signal processing circuit according to claim 1 , wherein the read comparison section obtains a matching ratio between the data value read in the reading processing and the predetermined data value, and
selects, as the delay time suitable for the access to the memory, an intermediate point of the delay time of the memory control clock with respect to the reference clock at a time when the matching ratio is highest.