Semiconductor device including a signal generator activated upon occurring of a timing signal
View Patent ↗A mode decode/latch circuit decodes an input signal based on a latch timing signal to output a test mode signal to a test execution circuit. Test mode signal line includes a high-resistance portion extending from the mode decode/latch circuit toward the vicinity of the test execution circuit and a low-resistance portion connecting together the distal end of the high-resistance portion and the input of the test execution circuit. A latch circuit for latching the test mode signal based on the latch timing signal is inserted in the low-resistance portion.
1. A semiconductor device comprising:
a signal generator for generating a specific signal at a timing specified by a timing signal;
a signal receiving circuit for receiving said specific signal to execute a specific operation specified by said specific signal;
a signal line for transferring said specific signal from said signal generator to said receiving circuit, said signal line including a first portion having a first end connected to said output of said signal generator and a second end, and a second portion having a resistance lower than a resistance of said first portion and connecting together said second end of said first portion and an input of said signal receiving circuit; and
a latch circuit inserted in said second portion to latch said specific signal at a timing specified by said timing signal.
2. The semiconductor device according to claim 1 , wherein said signal generator decodes an external input signal based on said timing specified by said timing signal to generate a mode signal as said specific signal.
3. The semiconductor device according to claim 1 , wherein said signal generator operates in a specific mode other than a normal operation mode of said semiconductor device.
4. The semiconductor device according to claim 3 , wherein said specific mode is a test mode of said semiconductor device.
5. The semiconductor device according to claim 1 , wherein said latch circuit includes a switching buffer for receiving said specific signal from said signal generator, to output said specific signal only during occurring of said timing signal, and a flip-flop for receiving said specific signal from said switching buffer to store therein said specific signal and output the same to said signal receiving circuit.
6. The semiconductor device according to claim 5 , wherein said switching buffer reverses said specified signal input from said signal generator and outputs said reversed specified signal during occurring of said timing signal, and stops output of said reversed specified signal during absence of said timing signal.
7. The semiconductor device according to claim 6 , wherein said flip-flop includes a first inverter for receiving an output of said switching buffer, and a second inverter for receiving an output of said first inverter to return the same to an input of said first inverter.