Semiconductor device including a fin-channel recess-gate MISFET
View Patent ↗A fin-channel recess-gate MISFET has a fin channel including a first portion configured by a portion of a silicon substrate and a second portion configured by a pair of silicon layers selectively grown on the silicon substrate. The first portion is disposed below the recess of the recess gate and above an isolation film of a STI structure formed on the silicon substrate. The second portion is disposed above the recess of the recess gate.
1. A method for manufacturing a semiconductor device comprising:
forming a dielectric film pattern having a specific thickness on silicon semiconductor substrate;
selectively etching said silicon semiconductor substrate by using said dielectric film pattern as an etching mask to form a trench;
depositing an isolation film within said trench;
selectively etching said dielectric film pattern to form a pair of openings exposing therethrough a portion of said silicon semiconductor substrate;
selectively growing a silicon semiconductor layer on said portion of said semiconductor substrate;
removing said dielectric film pattern having said pair of openings;
etching a top portion of said isolation film;
forming a gate insulation film on a surface portion of said silicon substrate and at least a portion of said selectively grown semiconductor layer; and
forming a gate electrode opposing said surface portion of said silicon semiconductor substrate and said selectively grown semiconductor layer with an intervention of said gate insulation film.
2. A method for manufacturing a semiconductor device comprising:
forming a dielectric film pattern having a specific thickness on a silicon substrate;
selectively etching the silicon substrate by using the dielectric film pattern as an etching mask to form a trench in the silicon substrate;
removing a part of the dielectric film pattern to form a pair of openings exposing therethrough a part of a surface of the silicon substrate;
selectively growing a silicon layer on the part of the surface of the silicon substrate by using a selective epitaxial process;
removing the dielectric film pattern by a wet etching process;
removing a top portion of the isolation film to expose at least the side surface of the grown silicon layer;
forming a gate insulation film; and
forming a gate electrode facing a part of a surface of the grown silicon layer and the silicon substrate, with the gate insulation film therebetween.
3. The method for manufacturing a semiconductor device according to claim 2 , wherein a part of a side surface of the trench formed in the silicon substrate is exposed after the step of removing the top portion of the isolation film.
4. The method for manufacturing a semiconductor device according to claim 2 , wherein a thickness of the grown silicon layer is substantially the same as the thickness of the dielectric film pattern.
5. The method for manufacturing a semiconductor device according to claim 2 , further comprising:
forming a sidewall insulation film on side surfaces of both the gate electrode and the grown silicon layer.
6. The method for manufacturing a semiconductor device according to claim 5 , further comprising:
forming a contact plug directly connected to a top surface of the growing silicon layer
7. The method for manufacturing a semiconductor device according to claim 2 , wherein the isolation film deposited within the trench is a silicon dioxide film.
8. The method for manufacturing a semiconductor device according to claim 7 , wherein the step of removing the top portion of the isolation film is performed by a wet etching process.