IP Library Granted Patent US 7,754,581
Granted Patent B2
US 7,754,581 · App. 11/956,560 · Granted Jul 13, 2010

Method for manufacturing a three-dimensional semiconductor device and a wafer used therein

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Quick Facts
Patent No.
US 7,754,581
App. No.
11/956,560
Granted
Jul 13, 2010
Kind
B2
Abstract

A method for manufacturing a semiconductor device includes the steps of forming first and second semiconductor wafers each including an array of chips and elongate electrodes, forming a groove on scribe lines separating the chips from one another; coating a surface of one of the semiconductor wafers with adhesive; bonding together the semiconductor wafers while allowing the groove to receive therein excessive adhesive; and heating the wafers to connect the elongate electrodes of both the semiconductor wafers.

Claims (30)

1. A method for manufacturing a semiconductor device comprising:

forming first and second semiconductor wafers each including therein a plurality of chips and an elongate electrode, said chips being separated from one another by a scribe line;

forming a groove on a surface of at least one of said semiconductor wafers along said scribe line;

coating said surface of said at least one of said semiconductor wafers or a surface of the other of said semiconductor wafers with first adhesive;

bonding together said first and second semiconductor wafers by using said first adhesive while allowing said groove to receive therein excessive adhesive; and

connecting together said elongate electrodes of said first and second semiconductor wafers.

2. The method according to claim 1 , wherein said groove forming uses a half-cut dicing technique.

3. The method according to claim 1 , wherein said groove has a larger cross-section than said scribe lines.

4. The method according to claim 1 , further comprising:

forming a third semiconductor wafer including therein a plurality of chips and an elongate electrode;

forming, on a surface of said third said semiconductor wafer, a groove along a scribe line separating said semiconductor chips from one another;

polishing an exposed surface of one of said first and second semiconductor wafers to expose an end of said elongate electrode;

forming a coupling terminal on said end of said elongate electrode;

coating said polished surface or a said surface of said third semiconductor wafer with second adhesive;

bonding together said third semiconductor wafer and said one of said semiconductor wafers having said exposed surface by using said second adhesive while allowing said groove to receive therein excessive adhesive; and

connecting together said elongate electrode of said third semiconductor wafer and said coupling terminal.

5. The method according to claim 4 , wherein said coupling terminal forming includes electroplating using a dry film to deposit a metallic film.

6. A method for manufacturing a semiconductor device comprising:

forming first and second semiconductor wafers each including therein a plurality of chips and an elongate electrode, said chips being separated from one another by a scribe line;

forming a groove on a surface of at least one of said semiconductor wafers along said scribe line;

coating said surface of said at least one of said semiconductor wafers or a surface of the other of said semiconductor wafers with first adhesive;

bonding together said first and second semiconductor wafers by using said first adhesive while allowing said groove to receive therein excessive adhesive;

connecting together said elongate electrodes of said first and second semiconductor wafers;

forming a third semiconductor wafer including therein a plurality of chips and an elongate electrode;

forming, on a surface of said third said semiconductor wafer, a groove along a scribe line separating said semiconductor chips from one another;

polishing an exposed surface of one of said first and second semiconductor wafers to expose an end of said elongate electrode;

forming a coupling terminal on said end of said elongate electrode;

coating said polished surface or a said surface of said third semiconductor wafer with second adhesive;

bonding together said third semiconductor wafer and said one of said semiconductor wafers having said exposed surface by using said second adhesive while allowing said groove to receive therein excessive adhesive; and

connecting together said elongate electrode of said third semiconductor wafer and said coupling terminal.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2014
From: ELPIDA MEMORY, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032645/0422 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 25, 2008
From: IKEDA, HIROAKI; ISHINO, MASAKAZU; TENMEI, HIROYUKI; KANDA, NAOYA; NAKA, YASUHIRO; NISHI, KUNIHIKO
To: ELPIDA MEMORY, INC.
Reel/Frame 020695/0852 →