Sharing non-sharable devices between an embedded controller and a processor in a computer system
View Patent ↗System and method for sharing a device, e.g., non-volatile memory, between a host processor and a microcontroller. In response to system state change to a first state wherein the microcontroller is assured safe access to the non-volatile memory (e.g., in response to power-on reset, system reset, sleep state, etc.), the microcontroller holds the system in the first state (e.g., system reset), and switches access to the non-volatile memory from the processor to the microcontroller. While the system is held in the first state, the microcontroller accesses the device (e.g., non-volatile memory), e.g., fetches program instructions/data from the non-volatile memory and loads the program instructions/data into a memory of the microcontroller. After the access, the microcontroller changes or allows change of the system state, e.g., switches access to the device, e.g., the non-volatile memory, from the microcontroller to the processor, and releases the system from the first state.
1. A system, comprising:
a non-volatile memory;
a processor; and
a microcontroller coupled to the non-volatile memory and to the processor, wherein the microcontroller is configured to:
in response to a change in system state to a first state wherein the microcontroller is assured safe access to the non-volatile memory, hold the system in the first state and switch access to the non-volatile memory from the processor to the microcontroller;
while the system is held in the first state, fetch program instructions or data from the non-volatile memory and load the program instructions or data into a memory of the microcontroller; and
after the program instructions or data have been loaded, switch access to the non-volatile memory from the microcontroller to the processor, and release the system from the first state.
2. The system of claim 1 , wherein the change in system state to the first state is performed by software.
3. The system of claim 1 , wherein the first state comprises one or more of:
a power on reset (POR) state;
a system reset state; or
a sleep state.
4. The system of claim 1 , wherein the program instructions or data comprise firmware code or data for the microcontroller.
5. The system of claim 1 , the microcontroller is a peripheral device controller for a computer system.
6. A method for sharing a non-volatile memory between a processor and a microcontroller in a system, comprising:
in response to a change in system state to a first state wherein the microcontroller is assured safe access to the non-volatile memory, holding the system in the first state and switching access to the non-volatile memory from the processor to the microcontroller;
while the system is held in the first state, fetching program instructions or data from the non-volatile memory and loading the program instructions or data into a memory of the microcontroller; and
after the program instructions or data have been loaded, switching access to the non-volatile memory from the microcontroller to the processor, and releasing the system from the first state.
7. The method of claim 6 , wherein the change in system state to the first state is performed by software.
8. The method of claim 6 , wherein the first state comprises one or more of:
a power on reset (POR) state;
a system reset state; or
a sleep state.
9. The method of claim 6 , wherein the program instructions or data comprise firmware code or data for the microcontroller.
10. The method of claim 6 , the microcontroller is a peripheral device controller for a computer system.
11. A system, comprising:
a non-volatile memory;
a processor; and
a microcontroller coupled to the non-volatile memory and to the processor, wherein the microcontroller is configured to:
in response to a power on reset, hold a system reset signal in a reset state, thereby prohibiting the processor from accessing the non-volatile memory;
while the system reset signal is held in the reset state, fetch program instructions or data from the non-volatile memory and load the program instructions or data into a memory of the microcontroller; and
after the program instructions or data have been loaded, permit the processor in the system access to the non-volatile memory, and release the system reset signal from the reset state.
12. The system of claim 11 , wherein the program instructions or data comprise firmware code or data for the microcontroller.
13. The system of claim 12 , the microcontroller is a peripheral device controller for a computer system.
14. The system of claim 11 , wherein the microcontroller is coupled to the non-volatile memory via a non-volatile memory bus, and wherein the microcontroller is operable to fetch the program instructions or data from the non-volatile memory via the non-volatile memory bus.
15. The system of claim 14 , wherein the microcontroller is coupled to the processor via a host memory bus, and wherein the microcontroller is operable to switchably intercept or pass communications between the processor and the non-volatile memory.
16. The system of claim 15 , wherein the microcontroller comprises or is coupled to a switch, interposed between the non-volatile memory bus and the host memory bus, wherein the switch is controllable by the microcontroller to switchably intercept or pass communications between the processor and the non-volatile memory.
17. A method for sharing a non-volatile memory between a processor and a microcontroller in a system, comprising:
in response to a power on reset, holding a system reset signal in a reset state, thereby prohibiting the processor from accessing the non-volatile memory;
while the system reset signal is held in the reset state, fetching program instructions or data from the non-volatile memory and loading the program instructions or data into a memory of the microcontroller; and
after the program instructions or data have been loaded, permitting the processor in the system access to the non-volatile memory, and releasing the system reset signal from the reset state.
18. The method of claim 17 , wherein the program instructions or data comprise firmware code or data for the microcontroller.
19. The method of claim 17 , the microcontroller is a peripheral device controller for a computer system.
20. The method of claim 17 , wherein the microcontroller is coupled to the processor via a system reset bus, and wherein the microcontroller is operable to assert the system reset signal over the system reset bus.
21. The method of claim 17 , wherein the microcontroller is coupled to the non-volatile memory via a non-volatile memory bus, and wherein the microcontroller is operable to fetch the program instructions or data from the non-volatile memory via the non-volatile memory bus.
22. The method of claim 21 , wherein the microcontroller is coupled to the processor via a host memory bus, and wherein the microcontroller is operable switchably intercept or pass communications between the processor and the non-volatile memory.
23. The method of claim 22 , wherein the microcontroller comprises or is coupled to a switch, interposed between the non-volatile memory bus and the host memory bus, wherein the switch is controllable by the microcontroller to switchably intercept or pass communications between the processor and the non-volatile memory.