Method of forming an electronic device
A process of forming an electronic device including forming a first ultraviolet (“UV”) blocking layer over a conductive feature, wherein the first UV blocking layer lies within 90 nm of the conductive structure; forming a first insulating layer over the first UV blocking layer; and patterning the first insulating layer and the first UV blocking layer to form a first opening extending to the conductive feature, wherein during the process, the first UV blocking layer is exposed to UV radiation.
1. A process of forming an electronic device comprising:
forming a first ultraviolet (“UV”) blocking layer over a conductive feature, wherein the first UV blocking layer lies within 90 nm of the conductive structure;
forming a first insulating layer over the first UV blocking layer;
patterning the first insulating layer and the first UV blocking layer to form a first opening extending to the conductive feature;
forming a second UV blocking layer over the first insulating layer;
forming a second insulating layer over the second UV blocking layer; and
patterning the second insulating layer and the second UV blocking layer to form a second opening, wherein a bottom of the second opening is spaced apart from the conductive feature,
wherein during the process, the first UV blocking layer is exposed to UV radiation.
2. The process of claim 1 , further comprising forming an antireflective layer over the first insulating layer, wherein patterning the first insulating layer and the first UV blocking layer comprises patterning the antireflective layer.
3. The process of claim 1 , wherein the first insulating layer is at least 4 times thicker than the first UV blocking layer.
4. The process of claim 1 , further comprising:
forming a conductive layer over the first insulating layer and within the first opening; and
removing a portion of the conductive layer lying outside the first opening to form a conductive structure that is electrically connected to the conductive feature.
5. The process of claim 1 , wherein each of the first opening and the second opening overlies the conductive feature.
6. The process of claim 5 , further comprising:
forming a conductive layer over the second insulating layer and within the first opening and the second opening; and
removing a portion of the conductive layer overlying outside the second insulating layer to form a conductive structure that is electrically connected to the conductive feature.
7. The process of claim 1 , wherein patterning the first insulating layer and the first UV blocking layer and patterning the second insulating layer and the second UV blocking layer comprises:
forming a first patterned resist layer over the second insulating layer, wherein the first patterned resist layer includes a third opening, and wherein from a top view, the third opening corresponds to a shape of the first opening;
etching the second insulating layer and the second UV blocking layer to form a fourth opening overlying the conductive feature;
forming a second patterned resist layer over the second insulating layer, wherein the second patterned resist layer includes a fifth opening, and wherein from the top view, the fifth opening corresponds to a shape of the second opening; and
etching the first insulating layer, the first UV blocking layer, the second insulating layer, and the second UV blocking layer to form the first opening and the second opening.
8. The process of claim 1 , wherein patterning the first insulating layer and the first UV blocking layer and patterning the second insulating layer and the second UV blocking layer comprises:
forming a first patterned resist layer over the second insulating layer, wherein the first patterned resist layer includes a third opening, and wherein from a top view, the third opening corresponds to a shape of the second opening;
etching the second insulating layer and the second UV blocking layer to form the second opening;
forming a second patterned resist layer over the second insulating layer, wherein the second patterned resist layer includes a fourth opening, and wherein from the top view, the fourth opening corresponds to a shape of the first opening; and
etching the first insulating layer and the first UV blocking layer to form the first opening.
9. The process of claim 1 , wherein:
the first UV blocking layer and the second UV blocking layer have substantially a first same composition; and
the first insulating layer and the second insulating layer have substantially a second same composition.
10. The process of claim 1 , wherein the first UV blocking layer includes a silicon-rich insulating layer.
11. The process of claim 10 , wherein patterning the first insulating layer and the first UV blocking layer comprises:
etching the first insulating layer using a first etching chemistry having a first fluorine concentration; and
etching the first UV blocking layer using a second etching chemistry having a second fluorine concentration that is greater than the first fluorine concentration.
12. The process of claim 1 , wherein patterning the first insulating layer and the first UV blocking layer is performed by plasma etching using a radio frequency in a range of 25 to 29 MHz.
13. The process of claim 1 , wherein forming the first insulating layer is performed using a plasma-enhanced chemical vapor deposition technique.
14. A process of forming an electronic device comprising:
forming a first ultraviolet UV blocking layer over a conductive feature, wherein the first UV blocking layer lies within 90 nm of the conductive structure;
forming a first insulating layer over the first UV blocking layer;
forming a second UV blocking layer over the first insulating layer;
forming a second insulating layer over the second UV blocking layer;
patterning the second insulating layer, second UV blocking layer, first insulating layer and the first UV blocking layer to form a first opening and a second opening, wherein:
the first opening extends to the conductive feature;
the second opening overlies the conductive feature, and a bottom of the second opening is spaced apart from the conductive feature; and
during patterning, the first UV blocking layer is exposed to UV radiation within a plasma generated using a radio frequency in a range of 25 to 29 MHz;
forming a conductive layer over the second insulating layer and within the first and second openings; and
polishing the conductive layer to remove a portion of the conductive layer lying outside the first and second openings to form a conductive structure that is electrically connected to the conductive feature.
15. The process of claim 14 , wherein each of the first UV blocking layer and the second UV blocking layer is a silicon-rich oxide, a silicon-rich nitride, a silicon-rich oxynitride, or any combination thereof.
16. The process of claim 14 , further comprising forming an antireflective layer over the first insulating layer, wherein patterning the second insulating layer, second UV blocking layer, first insulating layer and the first UV blocking layer comprises patterning the antireflective layer.