Non-volatile memory having multiple erase operations
View Patent ↗A non-volatile storage device ( 1 ) has non-volatile memory units (FARY 0 to FARY 3 ), buffer units (BMRY 0 to BMRY 3 ) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside. Consequently, it is possible to reduce the overhead of a data transfer for reading/writing data from/to the non-volatile storage device.
1. A nonvolatile memory structured on one semiconductor substrate, comprising:
a plurality of memory banks, each comprising a nonvolatile memory unit and a buffer unit;
a control circuit; and
an interface,
wherein the control circuit controls access to one or more of the plurality of memory banks in accordance with an arbitrary one of a plurality of instructions received from outside via the interface,
wherein when receiving a first erase instruction, the control circuit performs one of a one block erase operation or a plural block erase operation in response to whether one block is selected or plural blocks are selected before receiving the first erase instruction, and
wherein when receiving a second erase instruction, the control circuit erases data stored in all of the buffer units of the plurality of memory banks.
2. A nonvolatile memory according to claim 1 ,
wherein in response to receiving the first erase information the control circuit selects one or more blocks for erasing based on address information received from outside before receiving the first erase instruction, and
wherein in response to receiving the second erase instruction the control circuit erases data stored in all of the buffer units of the plurality of memory banks without receiving address information from outside.
3. A nonvolatile memory according to claim 2 ,
wherein the control circuit receives an address specifying instruction with each received address information, and selects the one or more blocks in accordance with the address specifying instruction.