Interpolation digital-to-analog converter

1. A digital-to-analog converter (DAC) comprising:

coarse interpolation DACs configured to produce a current range based on a digital signal; and

fine interpolation DACs configured to produce an output current that is based on the digital signal and that is within the current range produced by the coarse interpolation DACs;

wherein the coarse interpolation DACs comprise two DACs that are controlled based on a first subset of bits from the digital signal; and

wherein the fine interpolation DACs comprise two DACs that are controlled based on a second subset of bits from the digital signal.

2. The DAC of claim 1 , wherein the first subset of bits comprise more significant bits in the digital signal than the second subset of bits.

3. The DAC of claim 1 , wherein the coarse interpolation DACs comprise a first coarse interpolation DAC that is controlled directly by the first subset of bits, and a second coarse interpolation DAC that is controlled by sums or differences that are formed from the first subset of bits.

4. The DAC of claim 3 , wherein the fine interpolation DACs comprise a first fine interpolation DC that is controlled directly by the second subset of bits, and a second fine interpolation DAC that is controlled by a complement of the second subset of bits.

5. The DAC of claim 1 , wherein the output current produced by the fine interpolation DACs corresponds to an analog current for the digital signal.

6. A digital-to-analog converter (DAC) comprising:

coarse interpolation DACs configured to produce a current range based on an input digital signal;

fine interpolation DACs configured to produce an output current that is based an input digital signal and that is within the current range produced by the coarse interpolation DACs;

wherein the output current produced by the fine interpolation DACs corresponds to an analog current for the input digital signal;

a current source to supply current, the current source being capable of outputting a maximum current; and

circuitry to subtract the analog current from the maximum current to produce a DAC output.

7. A digital-to-analog converter (DAC) comprising:

coarse interpolation DACs configured to produce a current range based on an input digital signal; and

fine interpolation DACs configured to produce an output current that is based on an input digital signal and that is within the current range produced by the coarse interpolation DACs;

wherein the coarse interpolation DACs each comprises parallel-connected transistors for passing current from the fine interpolation DACs; and

wherein the fine interpolation DACs each comprises parallel-connected transistors for passing current from a current source to a corresponding coarse interpolation DAC.

8. A digital-to-analog converter (DAC) comprising:

coarse interpolation DACs configured to produce a current range based on an input digital signal;

fine interpolation DACs configured to produce an output current that is based on an input digital signal and that is within the current range produced by the coarse interpolation DACs;

wherein the DAC comprises an N-bit DAC, where N≧2; and

wherein each of the coarse interpolation DACs and the fine interpolation DACs comprises N transistors.

9. A digital-to-analog converter (DAC) comprising:

coarse interpolation DACs configured to produce a current range based on an input digital signal;

fine interpolation DACs configured to produce an output current that is based on an input digital signal and that is within the current range produced by the coarse interpolation DACs; and

circuitry to generate a complement of the output current, the complement of the output current being an output of the DAC.

10. An N-bit (N≧2) digital-to-analog converter (DAC) comprising:

first transistors that are controllable to pass current from a current source, the first transistors comprising N/2 pairs of transistors that are controlled based on a first set of N/2 bits of an input digital signal or a complement of the first set of N/2 bits;

second transistors that are controllable to pass current from the first transistors, the second transistors comprising N/2 pairs of transistors that are controlled based on a second set of N/2 bits of the input digital signal;

third transistors that are controllable to pass current from the current source, the third transistors comprising N/2 pairs of transistors that are controlled based on the complement of the first set of N/2 bits or by the first set of N/2 bits; and

fourth transistors that are controllable to pass current from the third transistors, the fourth transistors comprising N/2 pairs of transistors that are controlled based on the second set of N/2 bits with a value added thereto or subtracted therefrom.

11. The N-bit DAC of claim 10 , wherein at least one of the second transistors is configured to pass a first current and at least one of the fourth transistors is configured to pass a second current; and

wherein at least one of the first and third transistors are configured to pass currents between the first and second currents to produce an output of the N-bit DAC.

12. The N-bit DAC of claim 10 , wherein at least some of the fourth transistors are controlled by adding a value of one to the second set of N/2 bits.

13. The N-bit DAC of claim 10 , wherein each of the first, second, third, and fourth transistors comprises plural transistors that are connected in parallel and that are each sized to pass different amounts of current.

14. The N-bit DAC of claim 13 , wherein the plural transistor are sized in sequence so that a transistor at one end of the sequence passes most current and a transistor at another end of the sequence passes least current.

15. Automatic test equipment (ATE) comprising:

circuitry to provide digital control signals; and

a digital-to-analog converter (DAC) to convert the digital signals to analog form for transmission to a device under test (DUT);

wherein the DAC comprises:

coarse interpolation DACs configured to produce a current range; and

fine interpolation DACs configured to produce an output current that is within the current range produced by the coarse interpolation DACs;

wherein the DAC comprises an N-bit DAC; and

wherein the N-bit DAC comprises:

first transistors that are controllable to pass current from a current source, the first transistors comprising N/2 pairs of transistors that are controlled based on a first set of N/2 bits of an input digital signal or a complement of the first set of N/2 bits;

second transistors that are controllable to pass current from the first transistors, the second transistors comprising N/2 pairs of transistors that are controlled based on a second set of N/2 bits of the input digital signal;

third transistors that are controllable to pass current from the current source, the third transistors comprising N/2 pairs of transistors that arc controlled based on the complement of the first set of N/2 bits or by the first set of N/2 bits; and

fourth transistors that are controllable to pass current from the third transistors, the fourth transistors comprising N/2 pairs of transistors that are controlled based on the second set of N/2 bits with a value added or subtracted thereto.

16. The ATE of claim 15 , further comprising:

pin electronics to receive an analog test signal from the DUT, the analog test signal being in response to one or more of the digital signals converted to analog form by the DAC.

17. Automatic test equipment (ATE) comprising:

circuitry to provide digital control signals; and

a digital-to-analog converter (DAC) to convert the digital signals to analog form for transmission to a device under test (DUT);

wherein the DAC comprises:

coarse interpolation DACs configured to produce a current range; and

fine interpolation DACs configured to produce an output current that is within the current range produced by the coarse interpolation DACs;

wherein the coarse interpolation DACs comprise a first coarse interpolation DAC that is controlled directly by a first subset of bits, and a second coarse interpolation DAC that is controlled by sums or differences that are formed from the first subset of bits.

18. The ATE of claim 17 , wherein the fine interpolation DACs comprise a first fine interpolation DC that is controlled directly by a second subset of bits, and a second fine interpolation DAC that is controlled by a complement of the second subset of bits.

19. Automatic test equipment (ATE) comprising:

circuitry to provide digital control signals; and

a digital-to-analog converter (DAC) to convert the digital signals to analog form for transmission to a device under test (DUT);

wherein the DAC comprises:

coarse interpolation DACs configured to produce a current range; and

fine interpolation DACs configured to produce an output current that is within the current range produced by the coarse interpolation DACs; and

wherein the DAC is used for frequency tracking.

20. The DAC of claim 6 , wherein the coarse interpolation DACs comprise a first coarse interpolation DAC that is controlled directly by a first subset of bits, and a second coarse interpolation DAC that is controlled by sums or differences that are formed from the first subset of bits.

21. The DAC of claim 20 , wherein the fine interpolation DACs comprise a first fine interpolation DC that is controlled directly by a second subset of bits, and a second fine interpolation DAC that is controlled by a complement of the second subset of bits.

22. The DAC of claim 8 , wherein the coarse interpolation DACs comprise a first coarse interpolation DAC that is controlled directly by a first subset of bits, and a second coarse interpolation DAC that is controlled by sums or differences that are formed from the first subset of bits.

23. The DAC of claim 22 , wherein the fine interpolation DACs comprise a first fine interpolation DC that is controlled directly by a second subset of bits, and a second fine interpolation DAC that is controlled by a complement of the second subset of bits.

24. The DAC of claim 9 , wherein the coarse interpolation DACs comprise a first coarse interpolation DAC that is controlled directly by a first subset of bits, and a second coarse interpolation DAC that is controlled by sums or differences that are formed from the first subset of bits.

25. The DAC of claim 24 , wherein the fine interpolation DACs comprise a first fine interpolation DC that is controlled directly by a second subset of bits, and a second fine interpolation DAC that is controlled by a complement of the second subset of bits.

26. The ATE of claim 19 , wherein the coarse interpolation DACs comprise a first coarse interpolation DAC that is controlled directly by a first subset of bits, and a second coarse interpolation DAC that is controlled by sums or differences that are formed from the first subset of bits.

27. The ATE of claim 26 , wherein the fine interpolation DACs comprise a first fine interpolation DC that is controlled directly by a second subset of bits, and a second fine interpolation DAC that is controlled by a complement of the second subset of bits.